Datasheet Texas Instruments LMK03000 — 数据表

制造商Texas Instruments
系列LMK03000
Datasheet Texas Instruments LMK03000

集成VCO的精密时钟调节器

数据表

LMK03000 Family Precision Clock Conditioner with Integrated VCO datasheet
PDF, 1.1 Mb, 修订版: O, 档案已发布: Mar 15, 2013
从文件中提取

价格

状态

LMK03000CISQ/NOPBLMK03000CISQX/NOPBLMK03000DISQ/NOPBLMK03000DISQE/NOPBLMK03000DISQX/NOPBLMK03000ISQ/NOPBLMK03000ISQX/NOPB
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoYesYesNoNoNoNo

打包

LMK03000CISQ/NOPBLMK03000CISQX/NOPBLMK03000DISQ/NOPBLMK03000DISQE/NOPBLMK03000DISQX/NOPBLMK03000ISQ/NOPBLMK03000ISQX/NOPB
N1234567
Pin48484848484848
Package TypeRHSRHSRHSRHSRHSRHSRHS
Industry STD TermWQFNWQFNWQFNWQFNWQFNWQFNWQFN
JEDEC CodeS-PQFP-NS-PQFP-NS-PQFP-NS-PQFP-NS-PQFP-NS-PQFP-NS-PQFP-N
Package QTY2502500100025025002502500
CarrierSMALL T&RLARGE T&RLARGE T&RSMALL T&RLARGE T&RSMALL T&RLARGE T&R
Device MarkingK03000CIK03000CIK03000DIK03000DIK03000DIK03000 IK03000 I
Width (mm)7777777
Length (mm)7777777
Thickness (mm).75.75.75.75.75.75.75
Pitch (mm).5.5.5.5.5.5.5
Max Height (mm).8.8.8.8.8.8.8
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参数化

Parameters / ModelsLMK03000CISQ/NOPB
LMK03000CISQ/NOPB
LMK03000CISQX/NOPB
LMK03000CISQX/NOPB
LMK03000DISQ/NOPB
LMK03000DISQ/NOPB
LMK03000DISQE/NOPB
LMK03000DISQE/NOPB
LMK03000DISQX/NOPB
LMK03000DISQX/NOPB
LMK03000ISQ/NOPB
LMK03000ISQ/NOPB
LMK03000ISQX/NOPB
LMK03000ISQX/NOPB
Input LevelLVPECL, LVDS, LVCMOSLVPECL, LVDS, LVCMOSLVPECL, LVDS, LVCMOSLVPECL, LVDS, LVCMOSLVPECL, LVDS, LVCMOSLVPECL, LVDS, LVCMOSLVPECL, LVDS, LVCMOS
Number of Outputs9999999
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Frequency(Max), MHz1570157015701570157015701570
Output Frequency(Min), MHz0.290.290.290.290.290.290.29
Output LevelLVDS, LVPECL, RFLVDS, LVPECL, RFLVDS, LVPECL, RFLVDS, LVPECL, RFLVDS, LVPECL, RFLVDS, LVPECL, RFLVDS, LVPECL, RF
Package GroupWQFNWQFNWQFNWQFNWQFNWQFNWQFN
Package Size: mm2:W x L, PKG48WQFN: 49 mm2: 7 x 7(WQFN)48WQFN: 49 mm2: 7 x 7(WQFN)48WQFN: 49 mm2: 7 x 7(WQFN)48WQFN: 49 mm2: 7 x 7(WQFN)48WQFN: 49 mm2: 7 x 7(WQFN)48WQFN: 49 mm2: 7 x 7(WQFN)48WQFN: 49 mm2: 7 x 7(WQFN)
ProgrammabilityuWireuWireuWireuWireuWireuWireuWire
Special FeaturesDesign Tool AvailableDesign Tool AvailableDesign Tool AvailableDesign Tool AvailableDesign Tool AvailableDesign Tool AvailableDesign Tool Available
VCC Core, V3.33.33.33.33.33.33.3
VCC Out, V3.33.33.33.33.33.33.3

生态计划

LMK03000CISQ/NOPBLMK03000CISQX/NOPBLMK03000DISQ/NOPBLMK03000DISQE/NOPBLMK03000DISQX/NOPBLMK03000ISQ/NOPBLMK03000ISQX/NOPB
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliant

应用须知

  • AN-1865 Frequency Synthesis and Planning for PLL Architectures (Rev. C)
    PDF, 173 Kb, 修订版: C, 档案已发布: Apr 26, 2013
    This application report demonstrates the importance of understanding the least common multiple (LCM) and greatest common divisor (GCD).
  • AN-1821 CPRI Repeater System (Rev. A)
    PDF, 1.2 Mb, 修订版: A, 档案已发布: Apr 26, 2013
    This application report implements the Common Public Radio Interface (CPRI) for Remote Radio Heads(RRHs). The designer can use this application report for developing CPRI-based repeater systems inpoint-to-point or multi-hop configurations. This application report consists of:Designs for the CPRI SerDes Repeater Boards for the Radio Equipment (RE) and Radio EquipmentController (REC)
  • Phase Synchronization with Multiple Devices and Frequencies (Rev. A)
    PDF, 199 Kb, 修订版: A, 档案已发布: Apr 26, 2013
    This application note discusses how phase synchronization can be achieved when multiple chips are involved and also when the frequencies are not the same.
  • Generating Precision Clocks for Time- Interleaved ADCs
    PDF, 680 Kb, 档案已发布: Aug 2, 2007
  • High Speed ADCs with Interfacing, Driving and Clocking Schemes (Rev. A)
    PDF, 178 Kb, 修订版: A, 档案已发布: Apr 26, 2013
    This application report discusses how the performance of high-speed pipeline ADCs can be optimized bydesigning the right clock circuitry, a good analog input network, as well as how to get the data at thesehigh speeds undistorted from the ADC onto an FPGA or ASIC.
  • AN-2006 Synchronizing a DP83640 PTP Master to a GPS Receiver (Rev. A)
    PDF, 35 Kb, 修订版: A, 档案已发布: Apr 26, 2013
    This application report discusses methods of synchronizing the precision time protocol (PTP) clock to aGPS receiver using the DP83640 precision PHYTERв„ў.
  • AN-1734 Using the LMK03000C to Clean Recovered Clocks (Rev. B)
    PDF, 193 Kb, 修订版: B, 档案已发布: Apr 26, 2013
    This application note delivers an example of how to clean recovered clocks, using the SCAN25100 SERDES and LMK03000C clock conditioner.

模型线

制造商分类

  • Semiconductors> Clock and Timing> Clock Generators> General Purpose