Datasheet Texas Instruments LMK04002 — 数据表

LMK04000, LMK04001, LMK04002, LMK04010
LMK04011, LMK04031, LMK04033
www.ti.com SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011 LMK04000 Family Low-Noise Clock Jitter Cleaner with Cascaded PLLs
Check for Samples: LMK04000, LMK04001, LMK04002, LMK04010, LMK04011, LMK04031, LMK04033 FEATURES 1 23 Cascaded PLLatinumв„ў PLL Architecture
– PLL1
– Phase Detector Rate of up to 40 MHz
– Integrated Low-Noise Crystal Oscillator
Circuit
– Dual Redundant Input Reference Clock
with LOS
– PLL2
– Normalized [1 Hz] PLL Noise Floor of 224 dBc/Hz
– Phase Detector Rate up to 100 MHz
– Input Frequency-Doubler
– Integrated Low-Noise VCO
Ultra-Low RMS Jitter Performance
– 150 fs RMS Jitter (12 kHz – 20 MHz)
– 200 fs RMS Jitter (100 Hz – 20 MHz)
LVPECL/2VPECL, LVDS, and LVCMOS outputs Support Clock Rates up to 1080 MHz
Default Clock Output (CLKout2) at power up
Five Dedicated Channel Divider and Delay
Blocks
Pin Compatible Family of Clocking Devices …