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Documents LP2996A
SNOSCY7 – JUNE 2014 LP2996A DDR Termination Regulator
1 Features 3 Description The LP2996A linear regulator is designed to meet the
JEDEC SSTL-2 specifications for termination of DDRSDRAM. The device also supports DDR2, DDR3 and
DDR3L VTT bus termination with VDDQ min of 1.35V.
The device contains a high-speed operational
amplifier to provide excellent response to load
transients. The output stage prevents shoot through
while delivering 1.5A continuous current and transient
peaks up to 3A in the application as required for
DDR-SDRAM termination. The LP2996A also
incorporates a VSENSE pin to provide superior load
regulation and a VREF output as a reference for the
chipset and DIMMs. 1 1.35V Minimum VDDQ
Source and Sink Current
Low Output Voltage Offset
No External Resistors Required
Linear Topology …