Datasheet Texas Instruments OPA842 — 数据表

制造商Texas Instruments
系列OPA842
Datasheet Texas Instruments OPA842

宽带,低失真,单位增益稳定,电压反馈运算放大器

数据表

Wideband Low Distortion Unity-Gain Stable Voltage-Feedback Op Amp datasheet
PDF, 813 Kb, 修订版: D, 档案已发布: Sep 28, 2010
从文件中提取

价格

状态

OPA842IDOPA842IDBVROPA842IDBVRG4OPA842IDBVTOPA842IDBVTG4OPA842IDG4OPA842IDROPA842IDRG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNoNoNoYesYesNoYes

打包

OPA842IDOPA842IDBVROPA842IDBVRG4OPA842IDBVTOPA842IDBVTG4OPA842IDG4OPA842IDROPA842IDRG4
N12345678
Pin85555888
Package TypeDDBVDBVDBVDBVDDD
Industry STD TermSOICSOT-23SOT-23SOT-23SOT-23SOICSOICSOIC
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY75300030002502507525002500
CarrierTUBELARGE T&RLARGE T&RSMALL T&RSMALL T&RTUBELARGE T&RLARGE T&R
Device Marking842OAQIOAQIOAQIOAQI842842842
Width (mm)3.911.61.61.61.63.913.913.91
Length (mm)4.92.92.92.92.94.94.94.9
Thickness (mm)1.581.21.21.21.21.581.581.58
Pitch (mm)1.27.95.95.95.951.271.271.27
Max Height (mm)1.751.451.451.451.451.751.751.75
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参数化

Parameters / ModelsOPA842ID
OPA842ID
OPA842IDBVR
OPA842IDBVR
OPA842IDBVRG4
OPA842IDBVRG4
OPA842IDBVT
OPA842IDBVT
OPA842IDBVTG4
OPA842IDBVTG4
OPA842IDG4
OPA842IDG4
OPA842IDR
OPA842IDR
OPA842IDRG4
OPA842IDRG4
2nd Harmonic, dBc8080808080808080
3rd Harmonic, dBc9797979797979797
@ MHz55555555
Acl, min spec gain, V/V11111111
Additional FeaturesN/AN/AN/AN/AN/AN/AN/AN/A
ArchitectureBipolar,Voltage FBBipolar,Voltage FBBipolar,Voltage FBBipolar,Voltage FBBipolar,Voltage FBBipolar,Voltage FBBipolar,Voltage FBBipolar,Voltage FB
BW @ Acl, MHz350350350350350350350350
CMRR(Min), dB8585858585858585
CMRR(Typ), dB9595959595959595
GBW(Typ), MHz350350350350350350350350
Input Bias Current(Max), pA3500000035000000350000003500000035000000350000003500000035000000
Iq per channel(Max), mA20.820.820.820.820.820.820.820.8
Iq per channel(Typ), mA20.220.220.220.220.220.220.220.2
Number of Channels11111111
Offset Drift(Typ), uV/C44444444
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Current(Typ), mA100100100100100100100100
Package GroupSOICSOT-23SOT-23SOT-23SOT-23SOICSOICSOIC
Package Size: mm2:W x L, PKG8SOIC: 29 mm2: 6 x 4.9(SOIC)5SOT-23: 8 mm2: 2.8 x 2.9(SOT-23)5SOT-23: 8 mm2: 2.8 x 2.9(SOT-23)5SOT-23: 8 mm2: 2.8 x 2.9(SOT-23)5SOT-23: 8 mm2: 2.8 x 2.9(SOT-23)8SOIC: 29 mm2: 6 x 4.9(SOIC)8SOIC: 29 mm2: 6 x 4.9(SOIC)8SOIC: 29 mm2: 6 x 4.9(SOIC)
Rail-to-RailNoNoNoNoNoNoNoNo
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Slew Rate(Typ), V/us400400400400400400400400
Total Supply Voltage(Max), +5V=5, +/-5V=101212121212121212
Total Supply Voltage(Min), +5V=5, +/-5V=1077777777
Vn at 1kHz(Typ), nV/rtHz2.62.62.62.62.62.62.62.6
Vn at Flatband(Typ), nV/rtHz2.72.72.72.72.72.72.72.7
Vos (Offset Voltage @ 25C)(Max), mV1.21.21.21.21.21.21.21.2

生态计划

OPA842IDOPA842IDBVROPA842IDBVRG4OPA842IDBVTOPA842IDBVTG4OPA842IDG4OPA842IDROPA842IDRG4
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant

应用须知

  • RLC Filter Design for ADC Interface Applications (Rev. A)
    PDF, 299 Kb, 修订版: A, 档案已发布: May 13, 2015
    As high performance Analog-to-Digital Converters (ADCs) continue to improve in their performance, the last stage interface from the final amplifier into the converter inputs becomes a critical element in the system design if the full converter dynamic range is desired. This application note describes the performance and design equations for a simple passive 2nd-order filter used successfully in AD
  • Wideband Complementary Current Output DAC Single-Ended Interface
    PDF, 597 Kb, 档案已发布: Jun 21, 2005
    High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
  • ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC Drivers
    PDF, 273 Kb, 档案已发布: Apr 22, 2004
    Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation
  • Measuring Board Parasitics in High-Speed Analog Design
    PDF, 134 Kb, 档案已发布: Jul 7, 2003
    Successful circuit designs using high-speed amplifiers can depend upon understanding and identifying parasitic PCB components. Simulating a design while including PCB parasitics can protect against unpleasant production surprises. This application report discusses an easy method for measuring parasitic components in a prototype or final PC board design by using a standard oscilloscope and low freq
  • Noise Analysis for High Speed Op Amps (Rev. A)
    PDF, 256 Kb, 修订版: A, 档案已发布: Jan 17, 2005
    As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

模型线

制造商分类

  • Semiconductors> Amplifiers> Operational Amplifiers (Op Amps)> High-Speed Op Amps (>=50MHz)