NS16C552,PC16552D PC16552D Dual Universal Asynchronous Receiver/Transmitter with FIFOs†Literature Number: SNLS387B PC16552D
Dual Universal Asynchronous
Receiver/Transmitter with FIFOs ВІ
General Description Features The PC16552D is a dual version of the PC16550D Universal
Asynchronous Receiver/Transmitter (UART). The two serial
channels are completely independent except for a common
CPU interface and crystal input. On power-up both channels
are functionally identical to the 16450*. Each channel can
operate with on-chip transmitter and receiver FIFOs (FIFO
mode) to relieve the CPU of excessive software overhead.
In FIFO mode each channel is capable of buffering 16 bytes
(plus 3 bits of error data per byte in the RCVR FIFO) of data
in both the transmitter and receiver. All the FIFO control
logic is on-chip to minimize system overhead and maximize
system efficiency.
Signalling for DMA transfers is done through two pins per
channel (TXRDY and RXRDY). The RXRDY function is multiplexed on one pin with the OUT 2 and BAUDOUT functions. The CPU can select these functions through a new
register (Alternate Function Register).
Each channel performs serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM,
and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete
status of each channel at any time. Status information reported includes the type and condition of the transfer operations being performed by the DUART, as well as any error
conditions (parity, overrun, framing, or break interrupt). …
