SMV512K32-SP
www.ti.com SLVSA21I – JUNE 2011 – REVISED JANUARY 2014 16-Mb RADIATION-HARDENED SRAM
Check for Samples: SMV512K32-SP FEATURES 1 20-ns Read, 13.8-ns Write Through Maximum
Access Time
Functionally Compatible With Commercial
512K x 32 SRAM Devices
Built-In EDAC (Error Detection and Correction)
to Mitigate Soft Errors
Built-In Scrub Engine for Autonomous
Correction
CMOS Compatible Input and Output Level,
Three State Bidirectional Data Bus
– 3.3 ±0.3-V I/O, 1.8 ±0.15-V CORE (1)
(2)
(3)
(4) Radiation Performance (1)
– Uses Both Substrate Engineering and
Radiation Hardened by Design (HBD) (2)
– TID Immunity > 3e5 rad (Si)
– SER < 5e-17 Upsets/Bit-Day
(Core Using EDAC and Scrub) (3)
– Latch up immunity > LET = 110 MeV
(T = 398K) …
