SN54AHC74, SN74AHC74
www.ti.com SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013 Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
Check for Samples: SN54AHC74, SN74AHC74 FEATURES DESCRIPTION The ’AHC74 dual positive-edge-triggered devices are
D-type flip-flops. 1 Operating Range 2-V to 5.5-V VCC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101) A low level at the preset (PRE) or clear (CLR) inputs
sets or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not …
