Datasheet Texas Instruments SN65CML100DG4 — 数据表

SN65CML100
www.ti.com SLLS547 – NOVEMBER 2002 1.5-Gbps LVDS/LVPECL/CML-TO-CML TRANSLATOR/REPEATER
FEATURES DESCRIPTION Provides Level Translation From LVDS or
LVPECL to CML, Repeating From CML to CML
Signaling Rates(1) up to 1.5 Gbps
CML Compatible Output Directly Drives
Devices With 3.3-V, 2.5-V, or 1.8-V Supplies
Total Jitter < 70 ps
Low 100 ps (Max) Part-To-Part Skew
Wide Common-Mode Receiver Capability
Allows Direct Coupling of Input Signals
25 mV of Receiver Input Threshold Hysteresis
Over 0-V to 4-V Common-Mode Range
Propagation Delay Times, 800 ps Maximum
3.3-V Supply Operation
Available in SOIC and MSOP Packages APPLICATIONS Level Translation
622-MHz Central Office Clock Distribution
High-Speed Network Routing
Wireless Basestations
Low Jitter Clock Repeater (1) (1) The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second). A
B 8 4 2 7 …