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SLLSEH2B – SEPTEMBER 2013 – REVISED MARCH 2017 SN65DSI86 MIPI® DSI to eDP™ Bridge
1 Features 2 Applications 1 Embedded DisplayPortв„ў (eDPв„ў) 1.4 Compliant
Supporting 1, 2, or 4 Lanes at 1.62 Gbps (RBR),
2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24
Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
Implements MIPIВ® D-PHY Version 1.1 Physical
Layer Front-End and Display Serial Interface (DSI)
Version 1.02.00
Dual-Channel DSI Receiver Configurable for One,
Two, Three, or Four D-PHY Data Lanes Per
Channel Operating up to 1.5 Gbps Per Lane
Supports 18 bpp and 24 bpp DSI Video Packets
With RGB666 and RGB888 Formats
Suitable for 60 fps 4K 4096 Г— 2304 Resolution at
18 bpp Color, and WUXGA 1920 Г— 1200
Resolution with 3D Graphics at 60 fps (120 fps
Equivalent) …
