SN65ELT20
www.ti.com SLLS922A – DECEMBER 2008 – REVISED MARCH 2012 5-V TTL-to-Differential PECL Translator
Check for Samples: SN65ELT20 FEATURES 1 1.25-ns Maximum Propagation Delay
Operating Range: VCC = 4.2 V to 5.7 V With
GND = 0 V
Flow-Through Pinout Enables Easy Layout
Built-In Temperature Compensation
Drop-In Compatible With MC10ELT20,
MC100ELT20 PINOUT ASSIGNMENT
D-8, DGK-8 Package
(Top View) NC 1 Q 2 8 VCC 7 D TTL APPLICATIONS Data and Clock Transmission Over Backplane
Signaling Level Conversion for Clock or Data PECL
Q 3 6 NC NC 4 5 GND DESCRIPTION
The SN65ELT20 is a TTL-to-differential PECL
translator. It operates on a 5-V supply and ground
only. The output is undetermined when the inputs are
left floating. The low output skew makes the device
an ideal solution for clock or data signal translation. P0065-04 The SN65ELT20 is housed in an industry-standard
SOIC-8 package and is also available in a TSSOP-8
package. Table 1. Pin Description
PIN FUNCTION D TTL input Q,Q PECL outputs VCC Positive supply GND Ground ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE LEAD FINISH SN65ELT20D SN65ELT20 SOIC NiPdAu SN65ELT20DGK SN65ELT20 SOIC-TSSOP NiPdAu Leaded device options not initially available; contact a sales representative for further details. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. …
