SN65EPT23
SLLS969A – NOVEMBER 2009 – REVISED JANUARY 2011 www.ti.com 3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator
Check for Samples: SN65EPT23 FEATURES 1 Dual 3.3 V Differential LVPECL/LVDS to
LVTTL/LVCMOS Buffer Translator
24 mA LVTTL Ouputs
Operating Range
– VCC = 3.0 V to 3.6 V
– GND = 0 V
Support for Clock Frequencies > 300 MHz
2.0 ns Typical Propagation Delay
Built-in Temperature Compensation
Drop in Compatible to MC100EPT23 PINOUT ASSIGNMENT
+ D0 + 1 8 VCC 7 Q0 6 Q1 5 GND + D0 2
LVPECL
+ LVTTL 3 D1 + D1 4 APPLICATIONS Data and Clock Transmission Over Backplane
Signaling Level Conversion for Clock or Data Table 1. Pin Description
PIN FUNCTION DESCRIPTION Q0, Q1 LVTTL/LVCMOS Outputs The SN65EPT23 is a low power dual LVPECL/LVDS
to LVTTL/LVCMOS translator device. The device
includes circuitry to maintain inputs at Vcc/2 when left
open. The SN65EPT23 is housed in an industry
standard SOIC-8 package and is also available in
TSSOP-8 option. D0, D 0, D1, D 1 Differential LVPECL/LVDS/CML Inputs VCC Positive Supply GND Ground spacer
ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE LEAD FINISH SN65EPT23D/DR …
