Datasheet Texas Instruments SN65LVDM22PWG4 — 数据表

SN65LVDS22
SN65LVDM22
www.ti.com SLLS315C – DECEMBER 1998 – REVISED JUNE 2002 DUAL MULTIPLEXED LVDS REPEATERS
FEATURES Meets or Exceeds the Requirements of ANSI
TIA/EIA-644-1995 Standard
Designed for Clock Rates up to 200 MHz
(400 Mbps)
Designed for Data Rates up to 250 Mbps
Pin Compatible With SN65LVDS122 and
SN65LVDT122, 1.5 Gbps 2x2 Crosspoint
Switch From TI
ESD Protection Exceeds 12 kV on Bus Pins
Operates From a Single 3.3-V Supply
Low-Voltage Differential Signaling With
Output Voltages of 350 mV Into:
– 100-Ω Load (SN65LVDS22)
– 50-Ω Load (SN65LVDM22)
Propagation Delay Time; 4 ns Typ
Power Dissipation at 400 Mbps of 150 mW
Bus Pins Are High Impedance When Disabled
or With VCC Less Than 1.5 V
LVTTL Levels Are 5 V Tolerant
Open-Circuit Fail Safe Receiver DESCRIPTION …