Datasheet Texas Instruments SN65LVDS100 — 数据表

制造商	Texas Instruments
系列	SN65LVDS100

2 Gbps LVDS / LVPECL / CML到LVDS中继器/转换器

数据表

PDF, 1.6 Mb, 修订版: E, 档案已发布: Jul 20, 2015

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	SN65LVDS100D	SN65LVDS100DG4	SN65LVDS100DGK	SN65LVDS100DGKG4	SN65LVDS100DGKR	SN65LVDS100DGKRG4	SN65LVDS100DR	SN65LVDS100DRG4
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes	No	No	Yes	No	No	Yes	Yes

	SN65LVDS100D	SN65LVDS100DG4	SN65LVDS100DGK	SN65LVDS100DGKG4	SN65LVDS100DGKR	SN65LVDS100DGKRG4	SN65LVDS100DR	SN65LVDS100DRG4
N	1	2	3	4	5	6	7	8
Pin	8	8	8	8	8	8	8	8
Package Type	D	D	DGK	DGK	DGK	DGK	D	D
Industry STD Term	SOIC	SOIC	VSSOP	VSSOP	VSSOP	VSSOP	SOIC	SOIC
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	75	75	80	80	2500	2500	2500	2500
Carrier	TUBE	TUBE	TUBE	TUBE	LARGE T&R	LARGE T&R	LARGE T&R	LARGE T&R
Device Marking	DL100	DL100	AZK	AZK	AZK	AZK	DL100	DL100
Width (mm)	3.91	3.91	3	3	3	3	3.91	3.91
Length (mm)	4.9	4.9	3	3	3	3	4.9	4.9
Thickness (mm)	1.58	1.58	.97	.97	.97	.97	1.58	1.58
Pitch (mm)	1.27	1.27	.65	.65	.65	.65	1.27	1.27
Max Height (mm)	1.75	1.75	1.07	1.07	1.07	1.07	1.75	1.75
Mechanical Data	下载	下载	下载	下载	下载	下载	下载	下载

Parameters / Models	SN65LVDS100D	SN65LVDS100DG4	SN65LVDS100DGK	SN65LVDS100DGKG4	SN65LVDS100DGKR	SN65LVDS100DGKRG4	SN65LVDS100DR	SN65LVDS100DRG4
Device Type	Buffer	Buffer	Buffer	Buffer	Buffer	Buffer	Buffer	Buffer
ESD HBM, kV	5	5	5	5	5	5	5	5
Function	Repeater/Translator	Repeater/Translator	Repeater/Translator	Repeater/Translator	Repeater/Translator	Repeater/Translator	Repeater/Translator	Repeater/Translator
ICC(Max), mA	30	30	30	30	30	30	30	30
Input Signal	CML,LVDS,LVPECL	CML,LVDS,LVPECL	CML,LVDS,LVPECL	CML,LVDS,LVPECL	CML,LVDS,LVPECL	CML,LVDS,LVPECL	CML,LVDS,LVPECL	CML,LVDS,LVPECL
No. of Rx	1	1	1	1	1	1	1	1
No. of Tx	1	1	1	1	1	1	1	1
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Signal	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS
Package Group	SOIC	SOIC	VSSOP	VSSOP	VSSOP	VSSOP	SOIC	SOIC
Package Size: mm2:W x L, PKG	8SOIC: 29 mm2: 6 x 4.9(SOIC)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	8VSSOP: 15 mm2: 4.9 x 3(VSSOP)	8VSSOP: 15 mm2: 4.9 x 3(VSSOP)	8VSSOP: 15 mm2: 4.9 x 3(VSSOP)	8VSSOP: 15 mm2: 4.9 x 3(VSSOP)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	8SOIC: 29 mm2: 6 x 4.9(SOIC)
Protocols	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS	LVDS
Signaling Rate, Mbps	2000	2000	2000	2000	2000	2000	2000	2000

	SN65LVDS100D	SN65LVDS100DG4	SN65LVDS100DGK	SN65LVDS100DGKG4	SN65LVDS100DGKR	SN65LVDS100DGKRG4	SN65LVDS100DR	SN65LVDS100DRG4
RoHS	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant

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Signaling Rate vs. Distance for Differential Buffers
PDF, 420 Kb, 档案已发布: Jan 26, 2010
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DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
PDF, 135 Kb, 档案已发布: Feb 19, 2003
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AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
PDF, 417 Kb, 修订版: C, 档案已发布: Oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

系列: SN65LVDS100 (8)