Datasheet Texas Instruments SN65LVDS20DRFR — 数据表

SN65LVDS20
SN65LVP20
www.ti.com SLLS620A – JUNE 2004 – REVISED SEPTEMBER 2005 LVPECL AND LVDS REPEATER/TRANSLATOR WITH ENABLE
FEATURES Low-Voltage PECL Input and Low-Voltage
PECL or LVDS Outputs
Signaling Rates to 4 Gbps or Clock Rates
to 2 GHz
– 120-ps Output Transition Times
– Less than 45 ps Total Jitter
– Less than 630 ps Propagation Delay Times 2.5-V or 3.3-V Supply Operation
2-mm x 2-mm Small-Outline
No-Lead Package APPLICATIONS PECL-to-LVDS Translation
Data or Clock Signal Amplification DESCRIPTION
The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater.
The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and
repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low
radiated emissions and minimal added jitter.
The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the
SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input to EN enables the outputs. A
high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential
transmission lines with nominally 100-Ω characteristic impedance.
Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended
PECL input signals. When not used, VBB should be unconnected or open. …