Datasheet Texas Instruments SN65LVDS306 — 数据表

SN65LVDS306
www.ti.com SLLS765B – SEPTEMBER 2006 – REVISED FEBRUARY 2007 PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
FEATURES Serial Interface Technology
Compatible With FlatLinkв„ў3G Such as
SN65LVDS305
Supports Video Interfaces up to 24-Bit RGB
Data and 3 Control Bits Received Over One
SubLVDS Differential Line
SubLVDS Differential Voltage Levels
Up to 405-Mbps Data Throughput
Three Operating Modes to Conserve Power
– Active mode QVGA: 17 mW
– Typical Shutdown: 0.7 μW
– Typical Standby Mode: 27 μW Typical
Bus-Swap Function for PCB-Layout Flexibility
ESD Rating > 4 kV (HBM)
Pixel Clock Range of 4 MHz–15 MHz
Failsafe on all CMOS Inputs
Packaged in 5-mm Г— 5-mm MicroStar Junior
ОјBGAВ® With 0,5-mm Ball Pitch
Very Low EMI Meets SAE J1752/3 Kh-Spec APPLICATIONS The serial data and clock are received via
sub-low-voltage differential signalling (SubLVDS)
lines. The SN65LVDS306 supports three operating …