Datasheet Texas Instruments SN65LVDS308 — 数据表

SN65LVDS308
www.ti.com SLLS835 – MAY 2007 PROGRAMMABLE 27-BIT PARALLEL-TO-SERIAL RECEIVER
FEATURES FlatLink 3G Serial Interface Technology
Compatible With FlatLinkв„ў 3G Transmitters
Such as SN65LVDS307
Supports Video Interfaces up to 24-Bit RGB
Data and 3 Control Bits Received Over Two
Differential Data Lines
SubLVDS Differential Voltage Levels
Up to 810-Mbps Data Throughput
Three Operating Modes to Conserve Power
– Active mode VGA 60 fps: 17 mW
– Typical Shutdown: 0.7 µW
– Typical Standby Mode: 67 µW Typical
ESD Rating > 4 kV (HBM)
Pixel-Clock Range of 8 MHz–30 MHz
Failsafe on all CMOS Inputs
4-mm Г— 4-mm MicroStar Juniorв„ўВµBGAВ®
Package With 0,5-mm Ball Pitch
Very Low EMI When receiving, the PLL locks to the incoming clock,
CLK, and generates an internal high-speed clock at
the line rate of the data lines. The data is serially
loaded into a shift register using the internal …