Datasheet Texas Instruments SN65LVDS311YFFR — 数据表

SN65LVDS311
www.ti.com SLLSE31B – MAY 2010 – REVISED MARCH 2013 PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER
Check for Samples: SN65LVDS311 FEATURES 1 2.8 Г— 2.8mm package size
1.8V input signal swing
24-Bit RGB Data, 3 Control Bits, 1 Parity Bit
and 2 Reserved Bits Transmitted over 1, 2 or 3
Differential Lines
SubLVDS Differential Voltage Levels
Three Operating Modes to Conserve Power
– Active-Mode QVGA 17.4mW (typ)
– Active-Mode VGA 28.8mW (typ)
– Shutdown Mode ≈ 0.5μA (typ)
– Standby Mode ≈ 0.5μA (typ)
ESD Rating > 3kV (HBM)
Pixel Clock Range of 4MHz–65MHz
Failsafe on all CMOS Inputs
Typical Application: Cameras, Embedded
Computers When transmitting, the PLL locks to the incoming
pixel clock PCLK and generates an internal highspeed clock at the line rate of the data lines. The
parallel data is latched on the rising edge of PCLK.
The serialized data is presented on the serial outputs
D0, D1, D2 with a recreation of the Pixel clock PCLK
generated from the internal high-speed clock and …