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Software SN65LVDS324
SLLSED9B – NOVEMBER 2012 – REVISED JULY 2015 SN65LVDS324 1080p60 Image Sensor Receiver
1 Features 3 Description The SN65LVDS324 is a SubLVDS deserializer that
recovers words, detects sync codes, multiplies the
input DDR clock by a ratio, and outputs parallel
CMOS 1.8 V data on the rising clock edge. It bridges
the video stream interface between HD image
sensors made by leading manufacturers, to a format
that common processors can accept. The supported
pixel frequency is 18.5 MHz to 162 MHz — suitable
for resolutions from VGA to 1080p60. 1 Bridges the Interface Between Video Image
Sensors and Processors
Receives Aptina HiSPiв„ў, Panasonic LVDS, or
Sony LVDS Parallel; Outputs 1.8V CMOS with
10/12/14/16 Bits at 18.5 MHz to 162 MHz
SubLVDS Inputs Support Up To:
– Sony LVDS parallel:
– 10-bpp: 1620 Mbps …
