Datasheet Texas Instruments SN65LVDS386 — 数据表

制造商Texas Instruments
系列SN65LVDS386
Datasheet Texas Instruments SN65LVDS386

16通道LVDS接收器

数据表

High-Speed Differential Line Receivers. datasheet
PDF, 1.7 Mb, 修订版: I, 档案已发布: Jul 29, 2014
从文件中提取

价格

状态

SN65LVDS386DGGSN65LVDS386DGGG4SN65LVDS386DGGRSN65LVDS386DGGRG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNo

打包

SN65LVDS386DGGSN65LVDS386DGGG4SN65LVDS386DGGRSN65LVDS386DGGRG4
N1234
Pin64646464
Package TypeDGGDGGDGGDGG
Industry STD TermTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY252520002000
CarrierTUBETUBELARGE T&RLARGE T&R
Device MarkingLVDS386LVDS386LVDS386LVDS386
Width (mm)6.16.16.16.1
Length (mm)17171717
Thickness (mm)1.151.151.151.15
Pitch (mm).5.5.5.5
Max Height (mm)1.21.21.21.2
Mechanical Data下载下载下载下载

参数化

Parameters / ModelsSN65LVDS386DGG
SN65LVDS386DGG
SN65LVDS386DGGG4
SN65LVDS386DGGG4
SN65LVDS386DGGR
SN65LVDS386DGGR
SN65LVDS386DGGRG4
SN65LVDS386DGGRG4
Device TypeReceiverReceiverReceiverReceiver
ESD HBM, kV15151515
FunctionReceiverReceiverReceiverReceiver
ICC(Max), mA70707070
Input SignalLVDSLVDSLVDSLVDS
No. of Rx16161616
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85
Output SignalLVTTLLVTTLLVTTLLVTTL
Package GroupTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG64TSSOP: 138 mm2: 8.1 x 17(TSSOP)64TSSOP: 138 mm2: 8.1 x 17(TSSOP)64TSSOP: 138 mm2: 8.1 x 17(TSSOP)64TSSOP: 138 mm2: 8.1 x 17(TSSOP)
ProtocolsLVDSLVDSLVDSLVDS
Signaling Rate, Mbps250250250250

生态计划

SN65LVDS386DGGSN65LVDS386DGGG4SN65LVDS386DGGRSN65LVDS386DGGRG4
RoHSCompliantCompliantCompliantCompliant

应用须知

  • Using Signaling Rate and Transfer Rate (Rev. A)
    PDF, 258 Kb, 修订版: A, 档案已发布: Feb 7, 2005
    This document defines data signaling rate and data transfer rate, and it demonstrates the differences between them. Taking the SN65LVDS386 and SN65LVDS387 16-channellow-voltage differential (LVDS) line drivers and receivers with random parallel data of various bandwidths as an example, this document discusses the components that make up the system timing budget and presents empirical data on cro

模型线

制造商分类

  • Semiconductors> Interface> LVDS/M-LVDS/ECL/CML> LVDS PHY (<800Mbps)