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SLLSEE8B – SEPTEMBER 2013 – REVISED SEPTEMBER 2014 SN65LVDS822 Flatlink™ LVDS Receiver
1 Features 3 Description The SN65LVDS822 is an advanced FlatLinkв„ў lowvoltage differential signal (LVDS) receiver designed
on a modern CMOS process. The device has several
unique features, including three selectable CMOS
output slew rates, CMOS output voltage support of
1.8 V to 3.3 V, a pinout swap option, integrated
differential termination (configurable), an automatic
low-power mode, and deserialization modes of 4:27
and 2:27. The device is compatible with TI FlatLinkв„ў
transmitters
such
as
the
SN75LVDS83B,
SN65LVDS93A, and standard industry LVDS
transmitters that comply with TIA/EIA 644-A. 1 4:27 LVDS-to-CMOS Deserializer
Pixel Clock Range of 4 MHz to 54 MHz, for …
