SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
www.ti.com SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 HIGH-SPEED DIFFERENTIAL RECEIVERS
Check for Samples: SN65LVDS33, SN65LVDT33, SN65LVDS34, SN65LVDT34 FEATURES 1 (1) (1) 400-Mbps Signaling Rate and 200-Mxfr/s
Data Transfer Rate
Operates With a Single 3.3-V Supply
-4 V to 5 V Common-Mode Input Voltage
Range
Differential Input Thresholds B + 80 mV
+
_
Failsafe B > A + 80 mV
+
_ Window Comparator Figure 13. Receiver With Active Failsafe ECL/PECL-TO-LVTTL CONVERSION WITH TI's LVDS RECEIVER
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know of the established technology and that it is capable of high-speed
data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like Copyright © 2001–2004, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDS33 SN65LVDT33 SN65LVDS34 SN65LVDT34 13 SN65LVDS33, SN65LVDT33
SN65LVDS34, SN65LVDT34
SLLS490B – MARCH 2001 – REVISED NOVEMBER 2004 www.ti.com LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design
option, designers have been able to take advantage of LVDS by implementing a small resistor divider network at
the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver
(no divider network required) which can be connected directly to an ECL driver with only the termination bias
voltage required for ECL termination (VCC–2 V). …
