SN65MLVD048
www.ti.com SLLS903 – DECEMBER 2009 QUAD CHANNEL M-LVDS RECEIVERS
Check for Samples: SN65MLVD048 FEATURES 1 2 (1) Low-Voltage Differential 30-Ω to 55-Ω Line
Receivers for Signaling Rates(1) up to
250Mbps; Clock Frequencies up to 125MHz
Type-1 Receiver Incorporates 25 mV of Input
Threshold Hysteresis
Type-2 Receiver Provides 100 mV Offset
Threshold to Detect Open-Circuit and Idle-Bus
Conditions
Wide Receiver Input Common-Mode Voltage
Range, –1 V to 3.4 V, Allows 2 V of Ground
Noise
Meets or Exceeds the M-LVDS Standard
TIA/EIA-899 for Multipoint Topology
High Input Impedance when Vcc ≤ 1.5V
Enhanced ESD Protection: 7 kV HBM on all
pins
48-Pin 7 X 7 QFN (RGZ)
The signaling rate of a line is the number of voltage
transitions that are made per second, expressed in the units
bps (bits per second). APPLICATIONS Parallel Multipoint Data and Clock
Transmission via Backplanes and Cables …
