SN65MLVD2
SN65MLVD3
www.ti.com SLLS767 – NOVEMBER 2006 SINGLE M-LVDS RECEIVERS
FEATURES APPLICATIONS (1) Low-Voltage Differential 30-Ω to 55-Ω Line
Receivers for Signaling Rates(1) up to
250Mbps; Clock Frequencies up to 125MHz
SN65MLVD2 Type-1 Receiver Incorporates 25
mV of Input Threshold Hysteresis
SN65MLVD3 Type-2 Receiver Provides 100
mV Offset Threshold to Detect Open-Circuit
and Idle-Bus Conditions
Wide Receiver Input Common-Mode Voltage
Range, –1 V to 3.4 V, Allows 2 V of Ground
Noise
Improved VIT (35 mV)
Meets or Exceeds the M-LVDS Standard
TIA/EIA-899 for Multipoint Topology
High Input Impedance with Low Supply
Voltage
Bus-Pin HBM ESD Protection Exceeds 9 kV
Packaged in 8-Pin SON (DRB) 70% Smaller
Than 8-Pin SOIC Parallel Multipoint Data and Clock
Transmission via Backplanes and Cables …
