Datasheet Texas Instruments SN74ABT8543DW — 数据表

制造商	Texas Instruments
系列	SN74ABT8543
零件号	SN74ABT8543DW

使用八路注册总线收发器28-SOIC -40至85扫描测试设备

数据表

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PDF, 532 Kb, 修订版: E, 档案已发布: Jul 1, 1996

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价格

状态

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

打包

Pin	28
Package Type	DW
Industry STD Term	SOIC
JEDEC Code	R-PDSO-G
Package QTY	20
Carrier	TUBE
Device Marking	ABT8543
Width (mm)	7.5
Length (mm)	17.9
Thickness (mm)	2.35
Pitch (mm)	1.27
Max Height (mm)	2.65
Mechanical Data	下载

参数化

Bits	8
F @ Nom Voltage(Max)	150 Mhz
ICC @ Nom Voltage(Max)	38 mA
Operating Temperature Range	-40 to 85 C
Output Drive (IOL/IOH)(Max)	64/-32 mA
Package Group	SOIC
Package Size: mm2:W x L	28SOIC: 184 mm2: 10.3 x 17.9(SOIC) PKG
Rating	Catalog
Technology Family	ABT
VCC(Max)	5.5 V
VCC(Min)	4.5 V
Voltage(Nom)	5 V
tpd @ Nom Voltage(Max)	5.8 ns

生态计划

RoHS

Compliant

应用须知

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Programming CPLDs Via the 'LVT8986 LASP
PDF, 819 Kb, 档案已发布: Nov 1, 2005
This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
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Quad Flatpack No-Lead Logic Packages (Rev. D)
PDF, 1.0 Mb, 修订版: D, 档案已发布: Feb 16, 2004
Texas Instruments (TI) Quad Flatpack No-lead (QFN) 14/16/20-terminal Pb-free plastic packages meet dimensions specified in JEDEC standard MO-241 allow for board miniaturization and hold several advantages over traditional SOIC SSOP TSSOP and TVSOP packages. The packages are physically smaller have a smaller routing area improved thermal performance and improved electrical parasitics while
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Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)
PDF, 528 Kb, 修订版: B, 档案已发布: Jun 1, 1997
The purpose of this document is to assist the designers of high-performance digital logic systems in using the advanced BiCMOS technology (ABT) logic family. Detailed electrical characteristics of these bus-interface devices are provided and tables and graphs have been included to compare specific parameters of the ABT family with those of other logic families. In addition typical data is provide
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Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)
PDF, 115 Kb, 修订版: A, 档案已发布: Mar 1, 1997
Advanced bus-interface logic (ABIL) products processed in submicron advanced BiCMOS technologies (ABT) address the specific end-equipment demands of workstations personal and portable computers and telecommunications markets. This document discusses ABIL as system bus interfaces the merits of ABT its I/O structure packaging and ABT products for end-equipment specific solutions.
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Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)
PDF, 80 Kb, 修订版: A, 档案已发布: Dec 1, 1996
This document shows the output skew for the ABT16254 ABT16952 and ABT16500A devices of the TI advanced BiCMOS (ABT) family. The data samples show which output skew is being examined where the data originates and how it is analyzed. Some errors present in the data are discussed. Skew curves at varying temperatures are given for the ABT16240 ABT16245 ABT16952 ABT16500A and ABT16249 devic
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Understanding Advanced Bus-Interface Products Design Guide
PDF, 253 Kb, 档案已发布: May 1, 1996
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Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
PDF, 209 Kb, 档案已发布: May 10, 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

模型线

系列: SN74ABT8543 (2)

SN74ABT8543DL SN74ABT8543DW

制造商分类

Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic