Datasheet Texas Instruments SN74ABTH18646A — 数据表

制造商Texas Instruments
系列SN74ABTH18646A
Datasheet Texas Instruments SN74ABTH18646A

使用18位收发器和寄存器扫描测试设备

数据表

Scan Test Devices With 18-Bit Transceivers And Registers datasheet
PDF, 696 Kb, 修订版: D, 档案已发布: Jul 1, 1996
从文件中提取

价格

状态

SN74ABTH18646APM
Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

SN74ABTH18646APM
N1
Pin64
Package TypePM
Industry STD TermLQFP
JEDEC CodeS-PQFP-G
Package QTY160
CarrierJEDEC TRAY (10+1)
Device MarkingABTH18646A
Width (mm)10
Length (mm)10
Thickness (mm)1.4
Pitch (mm).5
Max Height (mm)1.6
Mechanical Data下载

参数化

Parameters / ModelsSN74ABTH18646APM
SN74ABTH18646APM
Bits18
F @ Nom Voltage(Max), Mhz150
ICC @ Nom Voltage(Max), mA24
Operating Temperature Range, C-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-32
Package GroupLQFP
Package Size: mm2:W x L, PKG64LQFP: 144 mm2: 12 x 12(LQFP)
RatingCatalog
Technology FamilyABT
VCC(Max), V5.5
VCC(Min), V4.5
Voltage(Nom), V5
tpd @ Nom Voltage(Max), ns6

生态计划

SN74ABTH18646APM
RoHSCompliant

应用须知

  • Programming CPLDs Via the 'LVT8986 LASP
    PDF, 819 Kb, 档案已发布: Nov 1, 2005
    This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
  • Bus-Hold Circuit
    PDF, 418 Kb, 档案已发布: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
  • Quad Flatpack No-Lead Logic Packages (Rev. D)
    PDF, 1.0 Mb, 修订版: D, 档案已发布: Feb 16, 2004
    Texas Instruments (TI) Quad Flatpack No-lead (QFN) 14/16/20-terminal Pb-free plastic packages meet dimensions specified in JEDEC standard MO-241 allow for board miniaturization and hold several advantages over traditional SOIC SSOP TSSOP and TVSOP packages. The packages are physically smaller have a smaller routing area improved thermal performance and improved electrical parasitics while
  • Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)
    PDF, 528 Kb, 修订版: B, 档案已发布: Jun 1, 1997
    The purpose of this document is to assist the designers of high-performance digital logic systems in using the advanced BiCMOS technology (ABT) logic family. Detailed electrical characteristics of these bus-interface devices are provided and tables and graphs have been included to compare specific parameters of the ABT family with those of other logic families. In addition typical data is provide
  • Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)
    PDF, 115 Kb, 修订版: A, 档案已发布: Mar 1, 1997
    Advanced bus-interface logic (ABIL) products processed in submicron advanced BiCMOS technologies (ABT) address the specific end-equipment demands of workstations personal and portable computers and telecommunications markets. This document discusses ABIL as system bus interfaces the merits of ABT its I/O structure packaging and ABT products for end-equipment specific solutions.
  • Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)
    PDF, 80 Kb, 修订版: A, 档案已发布: Dec 1, 1996
    This document shows the output skew for the ABT16254 ABT16952 and ABT16500A devices of the TI advanced BiCMOS (ABT) family. The data samples show which output skew is being examined where the data originates and how it is analyzed. Some errors present in the data are discussed. Skew curves at varying temperatures are given for the ABT16240 ABT16245 ABT16952 ABT16500A and ABT16249 devic
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, 档案已发布: May 1, 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, 档案已发布: May 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

模型线

系列: SN74ABTH18646A (1)

制造商分类

  • Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic