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SN74ACT1073
16-BIT BUS-TERMINATION ARRAY
WITH BUS-HOLD FUNCTION
SCAS193A -MARCH 1992 -REVISED NOVEMBER 2002 D Designed to Ensure Defined Voltage Levels
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D DW OR NS PACKAGE
(TOP VIEW) on Floating Bus Lines in CMOS Systems
4.5-V to 5.5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Reduces Undershoot and Overshoot
Caused By Line Reflections
Repetitive Peak Forward
Current . IFRM = 100 mA
Inputs Are TTL-Voltage Compatible
Low Power Consumption (Like CMOS)
Center-Pin VCC and GND Configuration
Minimizes High-Speed Switching Noise …
