Datasheet Texas Instruments SN74ALVC125 — 数据表

制造商	Texas Instruments
系列	SN74ALVC125

具有三态输出的四路总线缓冲门

数据表

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PDF, 615 Kb, 修订版: H, 档案已发布: Sep 17, 2004

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价格

状态

	SN74ALVC125D	SN74ALVC125DE4	SN74ALVC125DG4	SN74ALVC125DGVR	SN74ALVC125DR	SN74ALVC125DRE4	SN74ALVC125DRG4	SN74ALVC125NSR	SN74ALVC125NSRE4	SN74ALVC125PW	SN74ALVC125PWE4	SN74ALVC125PWG4	SN74ALVC125PWR	SN74ALVC125PWRE4	SN74ALVC125PWRG4
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No	No	No	No	No	No	No	No	No	No	No	No

打包

	SN74ALVC125D	SN74ALVC125DE4	SN74ALVC125DG4	SN74ALVC125DGVR	SN74ALVC125DR	SN74ALVC125DRE4	SN74ALVC125DRG4	SN74ALVC125NSR	SN74ALVC125NSRE4	SN74ALVC125PW	SN74ALVC125PWE4	SN74ALVC125PWG4	SN74ALVC125PWR	SN74ALVC125PWRE4	SN74ALVC125PWRG4
N	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
Pin	14	14	14	14	14	14	14	14	14	14	14	14	14	14	14
Package Type	D	D	D	DGV	D	D	D	NS	NS	PW	PW	PW	PW	PW	PW
Industry STD Term	SOIC	SOIC	SOIC	TVSOP	SOIC	SOIC	SOIC	SOP	SOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	50	50	50	2000	2500	2500	2500	2000	2000	90	90	90	2000	2000	2000
Carrier	TUBE	TUBE	TUBE	LARGE T&R	LARGE T&R	LARGE T&R	LARGE T&R	LARGE T&R	LARGE T&R	TUBE	TUBE	TUBE	LARGE T&R	LARGE T&R	LARGE T&R
Device Marking	ALVC125	ALVC125	ALVC125	VA125	ALVC125	ALVC125	ALVC125	ALVC125	ALVC125	VA125	VA125	VA125	VA125	VA125	VA125
Width (mm)	3.91	3.91	3.91	4.4	3.91	3.91	3.91	5.3	5.3	4.4	4.4	4.4	4.4	4.4	4.4
Length (mm)	8.65	8.65	8.65	3.6	8.65	8.65	8.65	10.3	10.3	5	5	5	5	5	5
Thickness (mm)	1.58	1.58	1.58	1.05	1.58	1.58	1.58	1.95	1.95	1	1	1	1	1	1
Pitch (mm)	1.27	1.27	1.27	.4	1.27	1.27	1.27	1.27	1.27	.65	.65	.65	.65	.65	.65
Max Height (mm)	1.75	1.75	1.75	1.2	1.75	1.75	1.75	2	2	1.2	1.2	1.2	1.2	1.2	1.2
Mechanical Data	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载

参数化

Parameters / Models	SN74ALVC125D	SN74ALVC125DE4	SN74ALVC125DG4	SN74ALVC125DGVR	SN74ALVC125DR	SN74ALVC125DRE4	SN74ALVC125DRG4	SN74ALVC125NSR	SN74ALVC125NSRE4	SN74ALVC125PW	SN74ALVC125PWE4	SN74ALVC125PWG4	SN74ALVC125PWR	SN74ALVC125PWRE4	SN74ALVC125PWRG4
Bits	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4
F @ Nom Voltage(Max), Mhz	100	100	100	100	100	100	100	100	100	100	100	100	100	100	100
ICC @ Nom Voltage(Max), mA	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01	0.01
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24	-24/24
Package Group	SOIC	SOIC	SOIC	TVSOP	SOIC	SOIC	SOIC	SO	SO	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14TVSOP: 23 mm2: 6.4 x 3.6(TVSOP)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SO: 80 mm2: 7.8 x 10.2(SO)	14SO: 80 mm2: 7.8 x 10.2(SO)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No	No	No	No	No	No	No	No	No	No
Technology Family	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC	ALVC
VCC(Max), V	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6
VCC(Min), V	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65	1.65
Voltage(Nom), V	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3	1.8,2.5,2.7,3.3
tpd @ Nom Voltage(Max), ns	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8	5.3,3.2,3.1,2.8

生态计划

	SN74ALVC125D	SN74ALVC125DE4	SN74ALVC125DG4	SN74ALVC125DGVR	SN74ALVC125DR	SN74ALVC125DRE4	SN74ALVC125DRG4	SN74ALVC125NSR	SN74ALVC125NSRE4	SN74ALVC125PW	SN74ALVC125PWE4	SN74ALVC125PWG4	SN74ALVC125PWR	SN74ALVC125PWRE4	SN74ALVC125PWRG4
RoHS	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant

应用须知

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TI SN74ALVC16835 Component Specification Analysis for PC100
PDF, 43 Kb, 档案已发布: Aug 3, 1998
The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
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Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
PDF, 96 Kb, 修订版: A, 档案已发布: May 13, 1998
Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
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16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
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Understanding Advanced Bus-Interface Products Design Guide
PDF, 253 Kb, 档案已发布: May 1, 1996
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Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
PDF, 154 Kb, 修订版: A, 档案已发布: Sep 8, 1999
In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

模型线

系列: SN74ALVC125 (15)

SN74ALVC125D SN74ALVC125DE4 SN74ALVC125DG4 SN74ALVC125DGVR SN74ALVC125DR SN74ALVC125DRE4 SN74ALVC125DRG4 SN74ALVC125NSR SN74ALVC125NSRE4 SN74ALVC125PW SN74ALVC125PWE4 SN74ALVC125PWG4 SN74ALVC125PWR SN74ALVC125PWRE4 SN74ALVC125PWRG4

制造商分类

Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver