Datasheet Texas Instruments SN74ALVC16374 — 数据表
| 制造商 | Texas Instruments |
| 系列 | SN74ALVC16374 |
具有三态输出的16位边缘触发D类触发器
数据表
16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs (Rev. A)
PDF, 196 Kb, 修订版: A, 档案已发布: May 1, 1995
价格
状态
| SN74ALVC16374DGGR | SN74ALVC16374DL | SN74ALVC16374DLR | |
|---|---|---|---|
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) | Obsolete (Manufacturer has discontinued the production of the device) | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No | No | No |
打包
| SN74ALVC16374DGGR | SN74ALVC16374DL | SN74ALVC16374DLR | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 48 | 48 | 48 |
| Package Type | DGG | DL | DL |
| Industry STD Term | TSSOP | SSOP | SSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Width (mm) | 6.1 | 7.49 | 7.49 |
| Length (mm) | 12.5 | 15.88 | 15.88 |
| Thickness (mm) | 1.15 | 2.59 | 2.59 |
| Pitch (mm) | .5 | .635 | .635 |
| Max Height (mm) | 1.2 | 2.79 | 2.79 |
| Mechanical Data | 下载 | 下载 | 下载 |
生态计划
| SN74ALVC16374DGGR | SN74ALVC16374DL | SN74ALVC16374DLR | |
|---|---|---|---|
| RoHS | Not Compliant | Not Compliant | Not Compliant |
| Pb Free | No | No | No |
应用须知
- TI SN74ALVC16835 Component Specification Analysis for PC100PDF, 43 Kb, 档案已发布: Aug 3, 1998
The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T - Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)PDF, 96 Kb, 修订版: A, 档案已发布: May 13, 1998
Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large - 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa - Understanding Advanced Bus-Interface Products Design GuidePDF, 253 Kb, 档案已发布: May 1, 1996
- Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)PDF, 154 Kb, 修订版: A, 档案已发布: Sep 8, 1999
In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families
模型线
系列: SN74ALVC16374 (3)
制造商分类
- Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop