Datasheet Texas Instruments SN74ALVC244-EP — 数据表

制造商Texas Instruments
系列SN74ALVC244-EP
Datasheet Texas Instruments SN74ALVC244-EP

具有三态输出的增强型产品八路缓冲器/驱动器

数据表

SN74ALVC244-EP datasheet
PDF, 487 Kb, 修订版: A, 档案已发布: Sep 29, 2004
从文件中提取

价格

状态

SN74ALVC244IPWREPV62/04762-01XE
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNo

打包

SN74ALVC244IPWREPV62/04762-01XE
N12
Pin2020
Package TypePWPW
Industry STD TermTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY20002000
CarrierLARGE T&RLARGE T&R
Device MarkingVA244IEPVA244IEP
Width (mm)4.44.4
Length (mm)6.56.5
Thickness (mm)11
Pitch (mm).65.65
Max Height (mm)1.21.2
Mechanical Data下载下载

参数化

Parameters / ModelsSN74ALVC244IPWREP
SN74ALVC244IPWREP
V62/04762-01XE
V62/04762-01XE
Bits88
Input TypeLVTTLLVTTL
Operating Temperature Range, C-40 to 85-40 to 85
Output TypeLVTTLLVTTL
Package GroupTSSOPTSSOP
Package Size: mm2:W x L, PKG20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
RatingHiRel Enhanced ProductHiRel Enhanced Product
Schmitt TriggerNoNo
Technology FamilyALVCALVC
VCC(Max), V3.63.6
VCC(Min), V1.651.65
Voltage(Nom), V1.8,2.5,2.7,3.31.8,2.5,2.7,3.3

生态计划

SN74ALVC244IPWREPV62/04762-01XE
RoHSCompliantCompliant

应用须知

  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, 档案已发布: Aug 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, 修订版: A, 档案已发布: May 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, 修订版: A, 档案已发布: Sep 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

模型线

系列: SN74ALVC244-EP (2)

制造商分类

  • Semiconductors> Space & High Reliability> Logic Products> Buffers/Drivers/Transceivers> Buffer Drivers