Datasheet Texas Instruments SN74ALVCH162373LR — 数据表

制造商	Texas Instruments
系列	SN74ALVCH162373
零件号	SN74ALVCH162373LR

具有三态输出的16位透明D类锁存器48-SSOP -40至85

数据表

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PDF, 839 Kb, 修订版: A, 档案已发布: Oct 20, 2004

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价格

状态

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

打包

Pin	48
Package Type	DL
Industry STD Term	SSOP
JEDEC Code	R-PDSO-G
Package QTY	1000
Carrier	LARGE T&R
Device Marking	ALVCH162373
Width (mm)	7.49
Length (mm)	15.88
Thickness (mm)	2.59
Pitch (mm)	.635
Max Height (mm)	2.79
Mechanical Data	下载

参数化

3-State Output	Yes
Bits	16
F @ Nom Voltage(Max)	150 Mhz
ICC @ Nom Voltage(Max)	0.04 mA
Operating Temperature Range	-40 to 85 C
Output Drive (IOL/IOH)(Max)	12/-12 mA
Package Group	SSOP
Package Size: mm2:W x L	48SSOP: 164 mm2: 10.35 x 15.88(SSOP) PKG
Rating	Catalog
Schmitt Trigger	No
Technology Family	ALVC
VCC(Max)	3.6 V
VCC(Min)	1.65 V
Voltage(Nom)	1.8,2.5,2.7,3.3 V
tpd @ Nom Voltage(Max)	6.3,5.3,4.5,4 ns

生态计划

RoHS

Compliant

应用须知

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TI SN74ALVC16835 Component Specification Analysis for PC100
PDF, 43 Kb, 档案已发布: Aug 3, 1998
The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
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Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
PDF, 96 Kb, 修订版: A, 档案已发布: May 13, 1998
Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
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Bus-Hold Circuit
PDF, 418 Kb, 档案已发布: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
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16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
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Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
PDF, 154 Kb, 修订版: A, 档案已发布: Sep 8, 1999
In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families
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Understanding Advanced Bus-Interface Products Design Guide
PDF, 253 Kb, 档案已发布: May 1, 1996

模型线

系列: SN74ALVCH162373 (7)

74ALVCH162373DLG4 74ALVCH162373GRE4 74ALVCH162373GRG4 74ALVCH162373ZQLR SN74ALVCH162373DL SN74ALVCH162373GR SN74ALVCH162373LR

制造商分类

Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Latch