Datasheet Texas Instruments SN74AUC2G125 — 数据表
| 制造商 | Texas Instruments |
| 系列 | SN74AUC2G125 |
具有三态输出的双总线缓冲门
数据表
Dual Bus Buffer Gate With 3-State Outputs--SN74AUC2G125 datasheet
PDF, 958 Kb, 修订版: D, 档案已发布: Aug 8, 2007
从文件中提取
价格
状态
| SN74AUC2G125DCTR | SN74AUC2G125DCUR | SN74AUC2G125YZPR | |
|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | Yes | Yes |
打包
| SN74AUC2G125DCTR | SN74AUC2G125DCUR | SN74AUC2G125YZPR | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 8 | 8 | 8 |
| Package Type | DCT | DCU | YZP |
| Industry STD Term | SSOP | VSSOP | DSBGA |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-XBGA-N |
| Package QTY | 3000 | 3000 | 3000 |
| Carrier | LARGE T&R | LARGE T&R | LARGE T&R |
| Device Marking | R | U25R | UMN |
| Width (mm) | 2.8 | 2 | 2.25 |
| Length (mm) | 2.95 | 2.3 | 1.25 |
| Thickness (mm) | 1.29 | .85 | .31 |
| Pitch (mm) | .65 | .5 | .5 |
| Max Height (mm) | 1.3 | .9 | .5 |
| Mechanical Data | 下载 | 下载 | 下载 |
生态计划
| SN74AUC2G125DCTR | SN74AUC2G125DCUR | SN74AUC2G125YZPR | |
|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant |
应用须知
- Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus DevicesPDF, 374 Kb, 档案已发布: Mar 21, 2003
System designers are continuously seeking ways to improve signal integrity, increase speed, and reduce power consumption in personal computers, telecommunication equipment, and other electronic systems. The Texas Instruments (TI) next-generation Advanced Ultra-low-voltage CMOS (AUC) octals and Widebus(TM) devices are designed to achieve these goals. These devices are designed for a 0.8-V to 2.7-V
模型线
系列: SN74AUC2G125 (3)
制造商分类
- Semiconductors> Logic> Little Logic