Datasheet Texas Instruments SN74CBT16244 — 数据表

制造商Texas Instruments
系列SN74CBT16244
Datasheet Texas Instruments SN74CBT16244

16位FET总线开关

数据表

16-Bit FET Bus Switches datasheet
PDF, 740 Kb, 修订版: I, 档案已发布: Oct 23, 2000
从文件中提取

价格

状态

SN74CBT16244DGGRSN74CBT16244DGVRSN74CBT16244DLSN74CBT16244DLG4SN74CBT16244DLR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNo

打包

SN74CBT16244DGGRSN74CBT16244DGVRSN74CBT16244DLSN74CBT16244DLG4SN74CBT16244DLR
N12345
Pin4848484848
Package TypeDGGDGVDLDLDL
Industry STD TermTSSOPTVSOPSSOPSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY2000200025251000
CarrierLARGE T&RLARGE T&RTUBETUBELARGE T&R
Device MarkingCBT16244CY244CBT16244CBT16244CBT16244
Width (mm)6.14.47.497.497.49
Length (mm)12.59.715.8815.8815.88
Thickness (mm)1.151.052.592.592.59
Pitch (mm).5.4.635.635.635
Max Height (mm)1.21.22.792.792.79
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参数化

Parameters / ModelsSN74CBT16244DGGR
SN74CBT16244DGGR
SN74CBT16244DGVR
SN74CBT16244DGVR
SN74CBT16244DL
SN74CBT16244DL
SN74CBT16244DLG4
SN74CBT16244DLG4
SN74CBT16244DLR
SN74CBT16244DLR
Bandwidth, MHz200200200200200
Configuration1:1 SPST1:1 SPST1:1 SPST1:1 SPST1:1 SPST
Input/Ouput Voltage(Max), V5.55.55.55.55.5
Input/Output Continuous Current(Max), mA128128128128128
Input/Output OFF-state Capacitance(Typ), pF4.54.54.54.54.5
Number of Channels1616161616
OFF-state leakage current(Max), µA11111
ON-state leakage current(Max), µA11111
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Package GroupTSSOPTVSOPSSOPSSOPSSOP
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TVSOP: 62 mm2: 6.4 x 9.7(TVSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)
RatingCatalogCatalogCatalogCatalogCatalog
Ron(Max), Ohms2020202020
Ron(Typ), Ohms55555
Supply Current(Max), uA33333
Supply Range, Max5.55.55.55.55.5
VIH(Min), V22222
VIL(Max), V0.80.80.80.80.8
Vdd(Max), V5.55.55.55.55.5
Vdd(Min), V44444
Vss(Max), VN/AN/AN/AN/AN/A
Vss(Min), VN/AN/AN/AN/AN/A

生态计划

SN74CBT16244DGGRSN74CBT16244DGVRSN74CBT16244DLSN74CBT16244DLG4SN74CBT16244DLR
RoHSCompliantCompliantCompliantCompliantCompliant

应用须知

  • Flexible Voltage-Level Translation With CBT Family Devices
    PDF, 40 Kb, 档案已发布: Jul 20, 1999
    Voltage translation between buses with incompatible logic levels can be accomplished using Texas Instruments (TI) translation-voltage clamps (TVC) or standard crossbar technology (CBT) devices. CBT devices in this application offer flexibility in designs, protection of circuits that are sensitive to high-state voltage-level overshoots, and cost efficiency.
  • 5-V To 3.3-V Translation With the SN74CBTD3384 (Rev. B)
    PDF, 35 Kb, 修订版: B, 档案已发布: Mar 1, 1997
    The emergence of low-voltage technology required existing 5-V systems to interact with 3.3-V systems. Compatibility issues of mixed-mode operation created the need for 5-V to 3.3-V translation. Buffers and transceivers serve as effective translators. While providing additional drive, these devices also add propagation delay and require directional control. In cases where additional drive is not
  • 3.3-V to 2.5-V Translation with Texas Instruments Crossbar Technology (Rev. A)
    PDF, 32 Kb, 修订版: A, 档案已发布: Apr 3, 1998
  • VOLTAGE LEVEL TRANSLATION (SL) - Family
    PDF, 111 Kb, 档案已发布: Sep 21, 2011
  • Bus FET Switch Solutions for Live Insertion Applications
    PDF, 300 Kb, 档案已发布: Feb 7, 2003
    In today?s competitive computing and networking industry, any equipment downtime due to component interconnects or bus failures impedes communication, hinders productivity and hampers financial growth. In recognizing this increasingly costly unplanned downtime, the industry introduced live-insertion technology to minimize the impact of any such failures. The live-insertion feature enables a networ
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa

模型线

制造商分类

  • Semiconductors> Switches and Multiplexers> Analog Switches/Muxes