Datasheet Texas Instruments SN74FB1653 — 数据表
| 制造商 | Texas Instruments |
| 系列 | SN74FB1653 |
具有缓冲时钟线的17位LVTTL / BTL通用存储收发器
数据表
价格
状态
| SN74FB1653PCA | |
|---|---|
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| SN74FB1653PCA | |
|---|---|
| N | 1 |
| Pin | 100 |
| Package Type | PCA |
| Industry STD Term | HLQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 90 |
| Carrier | JEDEC TRAY (10+1) |
| Device Marking | FB1653 |
| Width (mm) | 14 |
| Length (mm) | 14 |
| Thickness (mm) | 1.4 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.6 |
| Mechanical Data | 下载 |
参数化
| Parameters / Models | SN74FB1653PCA |
|---|---|
| Bits | 17 |
| F @ Nom Voltage(Max), Mhz | 90 |
| ICC @ Nom Voltage(Max), mA | 140 |
| Operating Temperature Range, C | 0 to 70 |
| Output Drive (IOL/IOH)(Max), mA | 100/-32 |
| Package Group | HLQFP |
| Package Size: mm2:W x L, PKG | 100HLQFP: 256 mm2: 16 x 16(HLQFP) |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | FB |
| VCC(Max), V | 5.5 |
| VCC(Min), V | 4.5 |
| Voltage(Nom), V | 5 |
| tpd @ Nom Voltage(Max), ns | 15.4 |
生态计划
| SN74FB1653PCA | |
|---|---|
| RoHS | Compliant |
应用须知
- Next-Generation BTL/Futurebus Transceivers Allow Single-Sided SMT Manufacturing (Rev. C)PDF, 65 Kb, 修订版: C, 档案已发布: Mar 1, 1997
BTL- and Futurebus-compatible transceivers and switching level meet the requirements of today?s high-speed data-communications and provide significant performance advantages over conventional backplane implementations. This document discusses the current and next generation of BTL/Futurebus Transceivers and the design trade-offs required when using these devices. - GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A)PDF, 184 Kb, 修订版: A, 档案已发布: Mar 1, 1997
GTL and BTL transceivers provide high-performance, excellent signal integrity and cost-effectiveness in high-speed backplane and point-to-point applications. This document discusses the GTL and BTL devices input/output (I/O) structure, power consumption, simultaneous switching, slew rate, and signal integrity. Design considerations for using these devices are provided. - Power-Up 3-State (PU3S) Circuits in TI Standard Logic DevicesPDF, 209 Kb, 档案已发布: May 10, 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
模型线
系列: SN74FB1653 (1)
制造商分类
- Semiconductors> Logic> Backplane Logic (GTL/TTL/BTL/ECL Transceiver/Translator)