Datasheet Texas Instruments SN74GTL2006PWR — 数据表
| 制造商 | Texas Instruments |
| 系列 | SN74GTL2006 |
| 零件号 | SN74GTL2006PWR |
13位GTL- / GTL / GTL +至LVTTL转换器28-TSSOP -40至85
数据表
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
打包
| Pin | 28 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | GK2006 |
| Width (mm) | 4.4 |
| Length (mm) | 9.7 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
生态计划
| RoHS | Compliant |
应用须知
- GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A)PDF, 184 Kb, 修订版: A, 档案已发布: Mar 1, 1997
GTL and BTL transceivers provide high-performance, excellent signal integrity and cost-effectiveness in high-speed backplane and point-to-point applications. This document discusses the GTL and BTL devices input/output (I/O) structure, power consumption, simultaneous switching, slew rate, and signal integrity. Design considerations for using these devices are provided. - Power-Up 3-State (PU3S) Circuits in TI Standard Logic DevicesPDF, 209 Kb, 档案已发布: May 10, 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
模型线
系列: SN74GTL2006 (1)
- SN74GTL2006PWR
制造商分类
- Semiconductors > Logic > Universal Bus Function > Universal Bus Transceiver (UBT)