Datasheet Texas Instruments SN74GTLPH306 — 数据表

制造商Texas Instruments
系列SN74GTLPH306
Datasheet Texas Instruments SN74GTLPH306

8位LVTTL至GTLP总线收发器

数据表

8-Bit LVTTL-to-GTL+ Bus Transceiver datasheet
PDF, 583 Kb, 修订版: E, 档案已发布: Aug 14, 2001
从文件中提取

价格

状态

74GTLPH306DGVRE4SN74GTLPH306DGVRSN74GTLPH306DWSN74GTLPH306DWRSN74GTLPH306PWSN74GTLPH306PWR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNoYesYesNoYes

打包

74GTLPH306DGVRE4SN74GTLPH306DGVRSN74GTLPH306DWSN74GTLPH306DWRSN74GTLPH306PWSN74GTLPH306PWR
N123456
Pin242424242424
Package TypeDGVDGVDWDWPWPW
Industry STD TermTVSOPTVSOPSOICSOICTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY20002000252000602000
CarrierLARGE T&RLARGE T&RTUBELARGE T&RTUBELARGE T&R
Device MarkingGH306GH306GTLPH306GTLPH306GH306GH306
Width (mm)4.44.47.57.54.44.4
Length (mm)5515.415.47.87.8
Thickness (mm)1.051.052.352.3511
Pitch (mm).4.41.271.27.65.65
Max Height (mm)1.21.22.652.651.21.2
Mechanical Data下载下载下载下载下载下载

参数化

Parameters / Models74GTLPH306DGVRE4
74GTLPH306DGVRE4
SN74GTLPH306DGVR
SN74GTLPH306DGVR
SN74GTLPH306DW
SN74GTLPH306DW
SN74GTLPH306DWR
SN74GTLPH306DWR
SN74GTLPH306PW
SN74GTLPH306PW
SN74GTLPH306PWR
SN74GTLPH306PWR
Bits888888
F @ Nom Voltage(Max), Mhz175175175175175175
ICC @ Nom Voltage(Max), mA202020202020
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA505050505050
Package GroupTVSOPTVSOPSOICSOICTSSOPTSSOP
Package Size: mm2:W x L, PKG24TVSOP: 32 mm2: 6.4 x 5(TVSOP)24TVSOP: 32 mm2: 6.4 x 5(TVSOP)24SOIC: 160 mm2: 10.3 x 15.5(SOIC)24SOIC: 160 mm2: 10.3 x 15.5(SOIC)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNo
Technology FamilyGTLPGTLPGTLPGTLPGTLPGTLP
VCC(Max), V3.453.453.453.453.453.45
VCC(Min), V3.153.153.153.153.153.15
Voltage(Nom), V3.33.33.33.33.33.3
tpd @ Nom Voltage(Max), ns7.57.57.57.57.57.5

生态计划

74GTLPH306DGVRE4SN74GTLPH306DGVRSN74GTLPH306DWSN74GTLPH306DWRSN74GTLPH306PWSN74GTLPH306PWR
RoHSCompliantCompliantCompliantCompliantCompliantCompliant

应用须知

  • Texas Instruments GTLP Frequently Asked Questions
    PDF, 496 Kb, 档案已发布: Jan 1, 2001
    Using a question-and-answer format, advantages of TI?s GTLP devices, particularly for backplane applications, are presented, as well as differences between GTLP and GTL/LVDS devices. Applicable topics include data throughput rates, synchronous clocks, price and alternative sources, bus transceivers, live insertion, power consumption, backplane termination, voltage translation, IBIS and HSPICE mode
  • Logic in Live-Insertion Applications With a Focus on GTLP
    PDF, 493 Kb, 档案已发布: Jan 14, 2002
    Live-insertion capability is an essential part of today?s high-speed data systems because those systems are expected to run continuously without being powered down. This application report delves into the cause and prevention of live-insertion and nanosecond-discontinuity effects, using both simulation and actual test measurements from a specially built GTLP EVM. Hypothetical cases for precharge c
  • Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP)
    PDF, 585 Kb, 档案已发布: Apr 5, 2001
    This application report compares two approaches for synchronous bus-system designs. The focus of the report is the comparison of a system using central-synchronous system clock (CSSC) with a system operated with a source-synchronous system clock (SSSC).The basic characteristics of lines, key factors that influence the bus line delay, and the impedance of bus lines are described.The theoretical
  • Fast GTLP Backplanes With the GTLPH1655 (Rev. A)
    PDF, 1.1 Mb, 修订版: A, 档案已发布: Sep 19, 2000
    This revision of the Fast GTL Backplanes With the GTL1655 application report addresses improvements, such as the improved OECE circuitry and implementation of theTexas Instruments TI-OPCE circuitry, that have been incorporated in the GTLPH1655 device. These improvements significantly improve signal integrity in distributed loads.This application report describes the physical principles of fast
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, 档案已发布: May 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

模型线

制造商分类

  • Semiconductors> Logic> Backplane Logic (GTL/TTL/BTL/ECL Transceiver/Translator)