Datasheet Texas Instruments SN74HC112 — 数据表
制造商 | Texas Instruments |
系列 | SN74HC112 |
具有清晰和预置功能的双路JK负边沿触发触发器
数据表
价格
状态
SN74HC112D | SN74HC112DE4 | SN74HC112DG4 | SN74HC112DR | SN74HC112DRG4 | SN74HC112DT | SN74HC112N | SN74HC112N3 | SN74HC112NE4 | |
---|---|---|---|---|---|---|---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Obsolete (Manufacturer has discontinued the production of the device) | Active (Recommended for new designs) |
Manufacture's Sample Availability | No | No | No | No | No | No | No | No | No |
打包
SN74HC112D | SN74HC112DE4 | SN74HC112DG4 | SN74HC112DR | SN74HC112DRG4 | SN74HC112DT | SN74HC112N | SN74HC112N3 | SN74HC112NE4 | |
---|---|---|---|---|---|---|---|---|---|
N | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
Pin | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
Package Type | D | D | D | D | D | D | N | N | N |
Industry STD Term | SOIC | SOIC | SOIC | SOIC | SOIC | SOIC | PDIP | PDIP | PDIP |
JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDIP-T | R-PDIP-T | R-PDIP-T |
Package QTY | 40 | 40 | 40 | 2500 | 2500 | 250 | 25 | 25 | |
Carrier | TUBE | TUBE | TUBE | LARGE T&R | LARGE T&R | SMALL T&R | TUBE | TUBE | |
Device Marking | HC112 | HC112 | HC112 | HC112 | HC112 | HC112 | SN74HC112N | SN74HC112N | |
Width (mm) | 3.91 | 3.91 | 3.91 | 3.91 | 3.91 | 3.91 | 6.35 | 6.35 | 6.35 |
Length (mm) | 9.9 | 9.9 | 9.9 | 9.9 | 9.9 | 9.9 | 19.3 | 19.3 | 19.3 |
Thickness (mm) | 1.58 | 1.58 | 1.58 | 1.58 | 1.58 | 1.58 | 3.9 | 3.9 | 3.9 |
Pitch (mm) | 1.27 | 1.27 | 1.27 | 1.27 | 1.27 | 1.27 | 2.54 | 2.54 | 2.54 |
Max Height (mm) | 1.75 | 1.75 | 1.75 | 1.75 | 1.75 | 1.75 | 5.08 | 5.08 | 5.08 |
Mechanical Data | 下载 | 下载 | 下载 | 下载 | 下载 | 下载 | 下载 | 下载 | 下载 |
参数化
Parameters / Models | SN74HC112D | SN74HC112DE4 | SN74HC112DG4 | SN74HC112DR | SN74HC112DRG4 | SN74HC112DT | SN74HC112N | SN74HC112N3 | SN74HC112NE4 |
---|---|---|---|---|---|---|---|---|---|
Approx. Price (US$) | 0.12 | 1ku | ||||||||
Bits | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | |
Bits(#) | 2 | ||||||||
F @ Nom Voltage(Max), Mhz | 70 | 70 | 70 | 70 | 70 | 70 | 70 | 70 | |
F @ Nom Voltage(Max)(Mhz) | 70 | ||||||||
ICC @ Nom Voltage(Max), mA | 0.04 | 0.04 | 0.04 | 0.04 | 0.04 | 0.04 | 0.04 | 0.04 | |
ICC @ Nom Voltage(Max)(mA) | 0.04 | ||||||||
Input Type | LVTTL/CMOS | ||||||||
Output Drive (IOL/IOH)(Max), mA | -4/4 | -4/4 | -4/4 | -4/4 | -4/4 | -4/4 | -4/4 | -4/4 | |
Output Drive (IOL/IOH)(Max)(mA) | -4/4 | ||||||||
Output Type | CMOS | ||||||||
Package Group | SOIC | SOIC | SOIC | SOIC | SOIC | SOIC | PDIP | PDIP | PDIP |
Package Size: mm2:W x L, PKG | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | 16SOIC: 59 mm2: 6 x 9.9(SOIC) | See datasheet (PDIP) | See datasheet (PDIP) | |
Package Size: mm2:W x L (PKG) | See datasheet (PDIP) | ||||||||
Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
Schmitt Trigger | No | No | No | No | No | No | No | No | No |
Technology Family | HC | HC | HC | HC | HC | HC | HC | HC | HC |
VCC(Max), V | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | |
VCC(Max)(V) | 6 | ||||||||
VCC(Min), V | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | |
VCC(Min)(V) | 2 | ||||||||
Voltage(Nom), V | 3.3,5 | 3.3,5 | 3.3,5 | 3.3,5 | 3.3,5 | 3.3,5 | 3.3,5 | 3.3,5 | |
Voltage(Nom)(V) | 3.3 5 | ||||||||
tpd @ Nom Voltage(Max), ns | 41 | 41 | 41 | 41 | 41 | 41 | 41 | 41 | |
tpd @ Nom Voltage(Max)(ns) | 41 |
生态计划
SN74HC112D | SN74HC112DE4 | SN74HC112DG4 | SN74HC112DR | SN74HC112DRG4 | SN74HC112DT | SN74HC112N | SN74HC112N3 | SN74HC112NE4 | |
---|---|---|---|---|---|---|---|---|---|
RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Not Compliant | Compliant |
Pb Free | Yes | No | Yes |
应用须知
- HCMOS Design Considerations (Rev. A)PDF, 207 Kb, 修订版: A, 档案已发布: Sep 9, 2002
This document describes a potential problem designers may encounter when using high-speed CMOS (HC) logic devices. There also is a broad range of CMOS-system to non-CMOS-system interfaces that need to be considered. The design engineer inevitably encounters these interfaces. Key considerations for handling these interfaces are also discussed in this book.
模型线
系列: SN74HC112 (9)
制造商分类
- Semiconductors> Logic> Flip-Flop/Latch/Register> J-K Flip-Flop