SN74LVCH32373A
32-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS www.ti.com SCAS618D – OCTOBER 1998 – REVISED MARCH 2005 FEATURES Member of the Texas Instruments Widebus+™
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.2 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
2 V at VCC = 3.3 V, TA = 25В°C
Ioff Supports Partial-Power-Down Mode
Operation Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A) DESCRIPTION/ORDERING INFORMATION
This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCH32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When …
