Datasheet Texas Instruments SN74LVT125 — 数据表

制造商	Texas Instruments
系列	SN74LVT125

具有三态输出的3.3V ABT四路总线缓冲器

数据表

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PDF, 673 Kb, 修订版: F, 档案已发布: Oct 13, 2003

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价格

状态

	SN74LVT125D	SN74LVT125DBLE	SN74LVT125DBR	SN74LVT125DBRG4	SN74LVT125DG4	SN74LVT125DR	SN74LVT125DRG4	SN74LVT125NSR	SN74LVT125PW	SN74LVT125PWG4	SN74LVT125PWLE	SN74LVT125PWR	SN74LVT125PWRG4
Lifecycle Status	NRND (Not recommended for new designs)	Obsolete (Manufacturer has discontinued the production of the device)	Active (Recommended for new designs)	Active (Recommended for new designs)	NRND (Not recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	NRND (Not recommended for new designs)	NRND (Not recommended for new designs)	NRND (Not recommended for new designs)	Obsolete (Manufacturer has discontinued the production of the device)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No	No	No	No	No	Yes	No	No	No	No

打包

	SN74LVT125D	SN74LVT125DBLE	SN74LVT125DBR	SN74LVT125DBRG4	SN74LVT125DG4	SN74LVT125DR	SN74LVT125DRG4	SN74LVT125NSR	SN74LVT125PW	SN74LVT125PWG4	SN74LVT125PWLE	SN74LVT125PWR	SN74LVT125PWRG4
N	1	2	3	4	5	6	7	8	9	10	11	12	13
Pin	14	14	14	14	14	14	14	14	14	14	14	14	14
Package Type	D	DB	DB	DB	D	D	D	NS	PW	PW	PW	PW	PW
Industry STD Term	SOIC	SSOP	SSOP	SSOP	SOIC	SOIC	SOIC	SOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	50		2000	2000	50	2500	2500	2000	90	90		2000	2000
Carrier	TUBE		LARGE T&R	LARGE T&R	TUBE	LARGE T&R	LARGE T&R	LARGE T&R	TUBE	TUBE		LARGE T&R	LARGE T&R
Device Marking	LVT125		LX125	LX125	LVT125	LVT125	LVT125	LVT125	LX125	LX125		LX125	LX125
Width (mm)	3.91	5.3	5.3	5.3	3.91	3.91	3.91	5.3	4.4	4.4	4.4	4.4	4.4
Length (mm)	8.65	6.2	6.2	6.2	8.65	8.65	8.65	10.3	5	5	5	5	5
Thickness (mm)	1.58	1.95	1.95	1.95	1.58	1.58	1.58	1.95	1	1	1	1	1
Pitch (mm)	1.27	.65	.65	.65	1.27	1.27	1.27	1.27	.65	.65	.65	.65	.65
Max Height (mm)	1.75	2	2	2	1.75	1.75	1.75	2	1.2	1.2	1.2	1.2	1.2
Mechanical Data	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载	下载

参数化

Parameters / Models	SN74LVT125D	SN74LVT125DBLE	SN74LVT125DBR	SN74LVT125DBRG4	SN74LVT125DG4	SN74LVT125DR	SN74LVT125DRG4	SN74LVT125NSR	SN74LVT125PW	SN74LVT125PWG4	SN74LVT125PWLE	SN74LVT125PWR	SN74LVT125PWRG4
Approx. Price (US$)		0.52 \| 1ku									0.52 \| 1ku
Bits	4		4	4	4	4	4	4	4	4		4	4
Bits(#)		4									4
F @ Nom Voltage(Max), Mhz	100		100	100	100	100	100	100	100	100		100	100
F @ Nom Voltage(Max)(Mhz)		100									100
ICC @ Nom Voltage(Max), mA	0.007		0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007		0.007	0.007
ICC @ Nom Voltage(Max)(mA)		0.007									0.007
Input Type		TTL/CMOS									TTL/CMOS
Operating Temperature Range, C	-40 to 85		-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85		-40 to 85	-40 to 85
Operating Temperature Range(C)		-40 to 85									-40 to 85
Output Drive (IOL/IOH)(Max), mA	-32/64		-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64		-32/64	-32/64
Output Drive (IOL/IOH)(Max)(mA)		-32/64									-32/64
Output Type		LVTTL									LVTTL
Package Group	SOIC	SSOP	SSOP	SSOP	SOIC	SOIC	SOIC	SOIC,SSOP,TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG	14SOIC: 52 mm2: 6 x 8.65(SOIC)		14SSOP: 48 mm2: 7.8 x 6.2(SSOP)	14SSOP: 48 mm2: 7.8 x 6.2(SSOP)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC),14SSOP: 48 mm2: 7.8 x 6.2(SSOP),14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)		14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
Package Size: mm2:W x L (PKG)		14TSSOP: 32 mm2: 6.4 x 5(TSSOP)									14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No	No	No	No	No	No	No	No
Technology Family	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT
VCC(Max), V	3.6		3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6		3.6	3.6
VCC(Max)(V)		3.6									3.6
VCC(Min), V	2.7		2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7		2.7	2.7
VCC(Min)(V)		2.7									2.7
Voltage(Nom), V	3.3		3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3		3.3	3.3
Voltage(Nom)(V)		3.3									3.3
tpd @ Nom Voltage(Max), ns	4		4	4	4	4	4	4	4	4		4	4
tpd @ Nom Voltage(Max)(ns)		4									4

生态计划

	SN74LVT125D	SN74LVT125DBLE	SN74LVT125DBR	SN74LVT125DBRG4	SN74LVT125DG4	SN74LVT125DR	SN74LVT125DRG4	SN74LVT125NSR	SN74LVT125PW	SN74LVT125PWG4	SN74LVT125PWLE	SN74LVT125PWR	SN74LVT125PWRG4
RoHS	Compliant	Not Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Not Compliant	Compliant	Compliant
Pb Free	No	No

应用须知

下载
LVT Family Characteristics (Rev. A)
PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, 档案已发布: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

模型线

系列: SN74LVT125 (13)

SN74LVT125D SN74LVT125DBLE SN74LVT125DBR SN74LVT125DBRG4 SN74LVT125DG4 SN74LVT125DR SN74LVT125DRG4 SN74LVT125NSR SN74LVT125PW SN74LVT125PWG4 SN74LVT125PWLE SN74LVT125PWR SN74LVT125PWRG4

制造商分类

Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver