Datasheet Texas Instruments SN74LVT573DW — 数据表
| 制造商 | Texas Instruments |
| 系列 | SN74LVT573 |
| 零件号 | SN74LVT573DW |
具有三态输出的3.3V ABT八路透明D类锁存器20-SOIC -40至85
数据表
价格
状态
| Lifecycle Status | NRND (Not recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 20 |
| Package Type | DW |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | LVT573 |
| Width (mm) | 7.5 |
| Length (mm) | 12.8 |
| Thickness (mm) | 2.35 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2.65 |
| Mechanical Data | 下载 |
替代品
| Replacement | SN74LVTH573DW |
| Replacement Code | Q |
生态计划
| RoHS | Compliant |
应用须知
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, 档案已发布: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
模型线
系列: SN74LVT573 (2)
- SN74LVT573DW SN74LVT573PWR
制造商分类
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Latch