Datasheet Texas Instruments SN74LVT8980ADWR — 数据表

制造商Texas Instruments
系列SN74LVT8980A
零件号SN74LVT8980ADWR
Datasheet Texas Instruments SN74LVT8980ADWR

具有8位通用主机接口的嵌入式测试总线控制器IEEE STD 1149.1(JTAG)TAP主设备24-SOIC -40至85

数据表

SN54LVT8980A, SN74LVT8980A datasheet
PDF, 865 Kb, 修订版: B, 档案已发布: Mar 18, 2004
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin24
Package TypeDW
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingLVT8980A
Width (mm)7.5
Length (mm)15.4
Thickness (mm)2.35
Pitch (mm)1.27
Max Height (mm)2.65
Mechanical Data下载

参数化

Bits8
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)64/-32 mA
Package GroupSOIC
Package Size: mm2:W x L24SOIC: 160 mm2: 10.3 x 15.5(SOIC) PKG
RatingCatalog
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V
tpd @ Nom Voltage(Max)30 ns

生态计划

RoHSCompliant

应用须知

  • Programming CPLDs Via the 'LVT8986 LASP
    PDF, 819 Kb, 档案已发布: Nov 1, 2005
    This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, 档案已发布: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

模型线

系列: SN74LVT8980A (3)

制造商分类

  • Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic