Datasheet Texas Instruments SN74LVT8980A — 数据表
| 制造商 | Texas Instruments |
| 系列 | SN74LVT8980A |
具有8位通用主机接口的嵌入式测试总线控制器IEEE STD 1149.1（JTAG）TAP主机
数据表
价格
状态
| SN74LVT8980ADW | SN74LVT8980ADWR | SN74LVT8980ADWRG4 | |
|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | No |
打包
| SN74LVT8980ADW | SN74LVT8980ADWR | SN74LVT8980ADWRG4 | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 24 | 24 | 24 |
| Package Type | DW | DW | DW |
| Industry STD Term | SOIC | SOIC | SOIC |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 25 | 2000 | 2000 |
| Carrier | TUBE | LARGE T&R | LARGE T&R |
| Device Marking | LVT8980A | LVT8980A | LVT8980A |
| Width (mm) | 7.5 | 7.5 | 7.5 |
| Length (mm) | 15.4 | 15.4 | 15.4 |
| Thickness (mm) | 2.35 | 2.35 | 2.35 |
| Pitch (mm) | 1.27 | 1.27 | 1.27 |
| Max Height (mm) | 2.65 | 2.65 | 2.65 |
| Mechanical Data | 下载 | 下载 | 下载 |
参数化
| Parameters / Models | SN74LVT8980ADW | SN74LVT8980ADWR | SN74LVT8980ADWRG4 |
|---|---|---|---|
| Bits | 8 | 8 | 8 |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Drive (IOL/IOH)(Max), mA | 64/-32 | 64/-32 | 64/-32 |
| Package Group | SOIC | SOIC | SOIC |
| Package Size: mm2:W x L, PKG | 24SOIC: 160 mm2: 10.3 x 15.5(SOIC) | 24SOIC: 160 mm2: 10.3 x 15.5(SOIC) | 24SOIC: 160 mm2: 10.3 x 15.5(SOIC) |
| Rating | Catalog | Catalog | Catalog |
| Technology Family | LVT | LVT | LVT |
| VCC(Max), V | 3.6 | 3.6 | 3.6 |
| VCC(Min), V | 2.7 | 2.7 | 2.7 |
| tpd @ Nom Voltage(Max), ns | 30 | 30 | 30 |
生态计划
| SN74LVT8980ADW | SN74LVT8980ADWR | SN74LVT8980ADWRG4 | |
|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant |
应用须知
- Programming CPLDs Via the 'LVT8986 LASPPDF, 819 Kb, 档案已发布: Nov 1, 2005
This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to - LVT Family Characteristics (Rev. A)PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, 档案已发布: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
模型线
系列: SN74LVT8980A (3)
制造商分类
- Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic