Datasheet Texas Instruments SN74LVTH162240 — 数据表

制造商	Texas Instruments
系列	SN74LVTH162240

具有三态输出的3.3V ABT 16位缓冲器/驱动器

数据表

PDF, 319 Kb, 修订版: F, 档案已发布: Nov 1, 2006

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	SN74LVTH162240DGGR	SN74LVTH162240DL	SN74LVTH162240DLR
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No

Parameters / Models	SN74LVTH162240DGGR	SN74LVTH162240DL	SN74LVTH162240DLR
Approx. Price (US$)		0.47 \| 1ku
Bits	16		16
Bits(#)		16
F @ Nom Voltage(Max), Mhz	160		160
F @ Nom Voltage(Max)(Mhz)		160
ICC @ Nom Voltage(Max), mA	0.005		0.005
ICC @ Nom Voltage(Max)(mA)		0.005
Operating Temperature Range, C	-40 to 85		-40 to 85
Operating Temperature Range(C)		-40 to 85
Output Drive (IOL/IOH)(Max), mA	-12/12		-12/12
Output Drive (IOL/IOH)(Max)(mA)		-12/12
Package Group	TSSOP	SSOP	SSOP
Package Size: mm2:W x L, PKG	48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)		48SSOP: 164 mm2: 10.35 x 15.88(SSOP)
Package Size: mm2:W x L (PKG)		48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)
Rating	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No
Technology Family	LVT	LVT	LVT
VCC(Max), V	3.6		3.6
VCC(Max)(V)		3.6
VCC(Min), V	2.7		2.7
VCC(Min)(V)		2.7
Voltage(Nom), V	3.3		3.3
Voltage(Nom)(V)		3.3
tpd @ Nom Voltage(Max), ns	4.6		4.6
tpd @ Nom Voltage(Max)(ns)		4.6

	SN74LVTH162240DGGR	SN74LVTH162240DL	SN74LVTH162240DLR
RoHS	Compliant	Compliant	Compliant
Pb Free	Yes

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LVT Family Characteristics (Rev. A)
PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, 档案已发布: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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Bus-Hold Circuit
PDF, 418 Kb, 档案已发布: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

系列: SN74LVTH162240 (3)