Datasheet Texas Instruments CLVTH162373MDLREP — 数据表

制造商	Texas Instruments
系列	SN74LVTH162373-EP
零件号	CLVTH162373MDLREP

具有三态输出的增强型产品3.3V Abt 16位透明D类锁存器48-SSOP -55至125

数据表

下载

PDF, 279 Kb, 修订版: A, 档案已发布: Jul 13, 2006

从文件中提取

价格

状态

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

打包

Pin	48
Package Type	DL
Industry STD Term	SSOP
JEDEC Code	R-PDSO-G
Package QTY	1000
Carrier	LARGE T&R
Device Marking	LVTH162373MEP
Width (mm)	7.49
Length (mm)	15.88
Thickness (mm)	2.59
Pitch (mm)	.635
Max Height (mm)	2.79
Mechanical Data	下载

参数化

3-State Output	Yes
Bits	16
F @ Nom Voltage(Max)	160 Mhz
ICC @ Nom Voltage(Max)	5 mA
Input Type	TTL
Operating Temperature Range	-55 to 125 C
Output Drive (IOL/IOH)(Max)	12/-12 mA
Output Type	TTL
Package Group	SSOP
Package Size: mm2:W x L	48SSOP: 164 mm2: 10.35 x 15.88(SSOP) PKG
Rating	HiRel Enhanced Product
Technology Family	LVT
VCC(Max)	3.6 V
VCC(Min)	2.7 V
tpd @ Nom Voltage(Max)	4.6 ns

生态计划

RoHS

Compliant

应用须知

下载
LVT Family Characteristics (Rev. A)
PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
下载
LVT-to-LVTH Conversion
PDF, 84 Kb, 档案已发布: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
下载
16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
下载
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
PDF, 105 Kb, 修订版: A, 档案已发布: Aug 1, 1997
The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
下载
Understanding Advanced Bus-Interface Products Design Guide
PDF, 253 Kb, 档案已发布: May 1, 1996
下载
Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
PDF, 209 Kb, 档案已发布: May 10, 2002
Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
下载
Power-Up Behavior of Clocked Devices (Rev. A)
PDF, 34 Kb, 修订版: A, 档案已发布: Feb 6, 2015

模型线

系列: SN74LVTH162373-EP (2)

CLVTH162373MDLREP V62/06654-01XE

制造商分类

Semiconductors > Space & High Reliability > Logic Products > Flip-Flop/Latch/Registers