Datasheet Texas Instruments SN74LVTH16245A-EP — 数据表

制造商Texas Instruments
系列SN74LVTH16245A-EP
Datasheet Texas Instruments SN74LVTH16245A-EP

具有三态输出的增强型产品3.3V Abt 16位总线收发器

数据表

SN74LVTH16245A-EP datasheet
PDF, 732 Kb, 修订版: G, 档案已发布: Oct 30, 2006
从文件中提取

价格

状态

8V16245AMDLREPG4CLVTH16245AMDLREPCLVTH16245AQDGGREPCLVTH16245AQDLREPV62/04602-01XEV62/04602-01YEV62/04602-02UAV62/04602-03XE
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNo

打包

8V16245AMDLREPG4CLVTH16245AMDLREPCLVTH16245AQDGGREPCLVTH16245AQDLREPV62/04602-01XEV62/04602-01YEV62/04602-02UAV62/04602-03XE
N12345678
Pin4848484848485648
Package TypeDLDLDGGDLDLDGGGQLDL
Industry STD TermSSOPSSOPTSSOPSSOPSSOPTSSOPBGA MICROSTAR JUNIORSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PBGA-NR-PDSO-G
Package QTY1000100020001000100020001000
CarrierLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&R
Device MarkingLVTH16245AEPLVTH16245AEPLH16245AEPLH16245AEPLH16245AEPLH16245AEPLVTH16245AEP
Width (mm)7.497.496.17.497.496.14.57.49
Length (mm)15.8815.8812.515.8815.8812.5715.88
Thickness (mm)2.592.591.152.592.591.15.752.59
Pitch (mm).635.635.5.635.635.5.65.635
Max Height (mm)2.792.791.22.792.791.212.79
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参数化

Parameters / Models8V16245AMDLREPG4
8V16245AMDLREPG4
CLVTH16245AMDLREP
CLVTH16245AMDLREP
CLVTH16245AQDGGREP
CLVTH16245AQDGGREP
CLVTH16245AQDLREP
CLVTH16245AQDLREP
V62/04602-01XE
V62/04602-01XE
V62/04602-01YE
V62/04602-01YE
V62/04602-02UA
V62/04602-02UA
V62/04602-03XE
V62/04602-03XE
Bits16161616161616
Bits(#)16
Operating Temperature Range, C-40 to 125,-55 to 125-40 to 125,-55 to 125-40 to 125,-55 to 125-40 to 125,-55 to 125-40 to 125,-55 to 125-40 to 125,-55 to 125-40 to 125,-55 to 125
Operating Temperature Range(C)-40 to 125
-40 to 85
-55 to 125
Package GroupSSOPSSOPTSSOPSSOPSSOPTSSOPBGA MICROSTAR JUNIORSSOP
Package Size: mm2:W x L, PKG48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)
Package Size: mm2:W x L (PKG)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)
RatingHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced Product
Schmitt TriggerNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.63.6
VCC(Max)(V)3.6
VCC(Min), V2.72.72.72.72.72.72.7
VCC(Min)(V)2.7

生态计划

8V16245AMDLREPG4CLVTH16245AMDLREPCLVTH16245AQDGGREPCLVTH16245AQDLREPV62/04602-01XEV62/04602-01YEV62/04602-02UAV62/04602-03XE
RoHSCompliantCompliantCompliantCompliantCompliantCompliantNot CompliantCompliant
Pb FreeNo

应用须知

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, 档案已发布: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Kb, 修订版: A, 档案已发布: Aug 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, 档案已发布: May 1, 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, 档案已发布: May 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

模型线

制造商分类

  • Semiconductors> Space & High Reliability> Logic Products> Buffers/Drivers/Transceivers> Transceivers