Datasheet Texas Instruments SN74LVTH16952 — 数据表

制造商	Texas Instruments
系列	SN74LVTH16952

具有三态输出的3.3 V ABT 16位寄存器收发器

数据表

PDF, 849 Kb, 修订版: G, 档案已发布: Apr 10, 2000

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	SN74LVTH16952DGGR	SN74LVTH16952DL	SN74LVTH16952DLG4	SN74LVTH16952DLR
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No

	SN74LVTH16952DGGR	SN74LVTH16952DL	SN74LVTH16952DLG4	SN74LVTH16952DLR
N	1	2	3	4
Pin	56	56	56	56
Package Type	DGG	DL	DL	DL
Industry STD Term	TSSOP	SSOP	SSOP	SSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Package QTY	2000	20	20	1000
Carrier	LARGE T&R	TUBE	TUBE	LARGE T&R
Device Marking	LVTH16952	LVTH16952	LVTH16952	LVTH16952
Width (mm)	6.1	7.49	7.49	7.49
Length (mm)	14	18.41	18.41	18.41
Thickness (mm)	1.15	2.59	2.59	2.59
Pitch (mm)	.5	.635	.635	.635
Max Height (mm)	1.2	2.79	2.79	2.79
Mechanical Data	下载	下载	下载	下载

Parameters / Models	SN74LVTH16952DGGR	SN74LVTH16952DL	SN74LVTH16952DLG4	SN74LVTH16952DLR
Bits	16	16	16	16
F @ Nom Voltage(Max), Mhz	160	160	160	160
ICC @ Nom Voltage(Max), mA	0.005	0.005	0.005	0.005
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	-32/64	-32/64	-32/64	-32/64
Package Group	TSSOP	SSOP	SSOP	SSOP
Package Size: mm2:W x L, PKG	56TSSOP: 113 mm2: 8.1 x 14(TSSOP)	56SSOP: 191 mm2: 10.35 x 18.42(SSOP)	56SSOP: 191 mm2: 10.35 x 18.42(SSOP)	56SSOP: 191 mm2: 10.35 x 18.42(SSOP)
Rating	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No
Technology Family	LVT	LVT	LVT	LVT
VCC(Max), V	3.6	3.6	3.6	3.6
VCC(Min), V	2.7	2.7	2.7	2.7
Voltage(Nom), V	3.3	3.3	3.3	3.3
tpd @ Nom Voltage(Max), ns	4	4	4	4

	SN74LVTH16952DGGR	SN74LVTH16952DL	SN74LVTH16952DLG4	SN74LVTH16952DLR
RoHS	Compliant	Compliant	Compliant	Compliant

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LVT Family Characteristics (Rev. A)
PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, 档案已发布: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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Bus-Hold Circuit
PDF, 418 Kb, 档案已发布: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

系列: SN74LVTH16952 (4)