Datasheet Texas Instruments SN74LVTH182504A — 数据表

制造商Texas Instruments
系列SN74LVTH182504A
Datasheet Texas Instruments SN74LVTH182504A

具有20位通用总线收发器的3.3V ABT扫描测试设备

数据表

3.3-V ABT Scan Test Devices With 20-Bit Universal Bus Transceivers datasheet
PDF, 923 Kb, 修订版: B, 档案已发布: Jun 1, 1997
从文件中提取

价格

状态

74LVTH182504APMG4SN74LVTH182504APM
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNo

打包

74LVTH182504APMG4SN74LVTH182504APM
N12
Pin6464
Package TypePMPM
Industry STD TermLQFPLQFP
JEDEC CodeS-PQFP-GS-PQFP-G
Package QTY160160
CarrierJEDEC TRAY (10+1)JEDEC TRAY (10+1)
Device MarkingLVTH182504ALVTH182504A
Width (mm)1010
Length (mm)1010
Thickness (mm)1.41.4
Pitch (mm).5.5
Max Height (mm)1.61.6
Mechanical Data下载下载

参数化

Parameters / Models74LVTH182504APMG4
74LVTH182504APMG4
SN74LVTH182504APM
SN74LVTH182504APM
Bits2020
F @ Nom Voltage(Max), Mhz160160
ICC @ Nom Voltage(Max), mA2727
Operating Temperature Range, C-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-3264/-32
Package GroupLQFPLQFP
Package Size: mm2:W x L, PKG64LQFP: 144 mm2: 12 x 12(LQFP)64LQFP: 144 mm2: 12 x 12(LQFP)
RatingCatalogCatalog
Technology FamilyLVTLVT
VCC(Max), V3.63.6
VCC(Min), V2.72.7
Voltage(Nom), V3.33.3
tpd @ Nom Voltage(Max), ns5.95.9

生态计划

74LVTH182504APMG4SN74LVTH182504APM
RoHSCompliantCompliant

应用须知

  • Programming CPLDs Via the 'LVT8986 LASP
    PDF, 819 Kb, 档案已发布: Nov 1, 2005
    This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, 档案已发布: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, 档案已发布: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Kb, 修订版: A, 档案已发布: Aug 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, 档案已发布: May 1, 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, 档案已发布: May 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features
  • Live Insertion
    PDF, 150 Kb, 档案已发布: Oct 1, 1996
    Many applications require the ability to exchange modules in electronic systems without removing the supply voltage from the module (live insertion). For example an electronic telephone exchange must always remain operational even during module maintenance and repair. To avoid damaging components additional circuitry modifications are necessary. This document describes in detail the phenomena tha
  • Input and Output Characteristics of Digital Integrated Circuits
    PDF, 1.7 Mb, 档案已发布: Oct 1, 1996
    This report contains a comprehensive collection of the input and output characteristic curves of typical integrated circuits from various logic families. These curves go beyond the information given in data sheets by providing additional details regarding the characteristics of the components. This knowledge is particularly useful when for example a decision must be made as to which circuit shou

模型线

系列: SN74LVTH182504A (2)

制造商分类

  • Semiconductors> Logic> Specialty Logic> Boundary Scan (JTAG) Logic