Datasheet Texas Instruments SN74LVTH182512DGGR — 数据表

制造商	Texas Instruments
系列	SN74LVTH182512
零件号	SN74LVTH182512DGGR

具有18位通用总线收发器的3.3V ABT扫描测试设备64-TSSOP -40至85

数据表

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PDF, 735 Kb, 修订版: B, 档案已发布: Oct 1, 1997

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价格

状态

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

打包

Pin	64
Package Type	DGG
Industry STD Term	TSSOP
JEDEC Code	R-PDSO-G
Package QTY	2000
Carrier	LARGE T&R
Device Marking	LVTH182512
Width (mm)	6.1
Length (mm)	17
Thickness (mm)	1.15
Pitch (mm)	.5
Max Height (mm)	1.2
Mechanical Data	下载

参数化

Bits	18
F @ Nom Voltage(Max)	160 Mhz
ICC @ Nom Voltage(Max)	24 mA
Operating Temperature Range	-40 to 85 C
Output Drive (IOL/IOH)(Max)	64/-32 mA
Package Group	TSSOP
Package Size: mm2:W x L	64TSSOP: 138 mm2: 8.1 x 17(TSSOP) PKG
Rating	Catalog
Technology Family	LVT
VCC(Max)	3.6 V
VCC(Min)	2.7 V
Voltage(Nom)	3.3 V
tpd @ Nom Voltage(Max)	5.7 ns

生态计划

RoHS

Compliant

应用须知

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Programming CPLDs Via the 'LVT8986 LASP
PDF, 819 Kb, 档案已发布: Nov 1, 2005
This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
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LVT Family Characteristics (Rev. A)
PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, 档案已发布: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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Bus-Hold Circuit
PDF, 418 Kb, 档案已发布: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

模型线

系列: SN74LVTH182512 (1)

SN74LVTH182512DGGR

制造商分类

Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic