Datasheet Texas Instruments SN74LVTH241 — 数据表
| 制造商 | Texas Instruments |
| 系列 | SN74LVTH241 |
具有三态输出的3.3V ABT八路缓冲器/驱动器
数据表
价格
状态
| SN74LVTH241DBR | SN74LVTH241DW | SN74LVTH241DWR | SN74LVTH241DWRG4 | SN74LVTH241PW | SN74LVTH241PWE4 | SN74LVTH241PWG4 | SN74LVTH241PWR | |
|---|---|---|---|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | No | No | No | No | No | No |
打包
| SN74LVTH241DBR | SN74LVTH241DW | SN74LVTH241DWR | SN74LVTH241DWRG4 | SN74LVTH241PW | SN74LVTH241PWE4 | SN74LVTH241PWG4 | SN74LVTH241PWR | |
|---|---|---|---|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
| Pin | 20 | 20 | 20 | 20 | 20 | 20 | 20 | 20 |
| Package Type | DB | DW | DW | DW | PW | PW | PW | PW |
| Industry STD Term | SSOP | SOIC | SOIC | SOIC | TSSOP | TSSOP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 2000 | 25 | 2000 | 2000 | 70 | 70 | 70 | 2000 |
| Carrier | LARGE T&R | TUBE | LARGE T&R | LARGE T&R | TUBE | TUBE | TUBE | LARGE T&R |
| Device Marking | LXH241 | LVTH241 | LVTH241 | LVTH241 | LXH241 | LXH241 | LXH241 | LXH241 |
| Width (mm) | 5.3 | 7.5 | 7.5 | 7.5 | 4.4 | 4.4 | 4.4 | 4.4 |
| Length (mm) | 7.2 | 12.8 | 12.8 | 12.8 | 6.5 | 6.5 | 6.5 | 6.5 |
| Thickness (mm) | 1.95 | 2.35 | 2.35 | 2.35 | 1 | 1 | 1 | 1 |
| Pitch (mm) | .65 | 1.27 | 1.27 | 1.27 | .65 | .65 | .65 | .65 |
| Max Height (mm) | 2 | 2.65 | 2.65 | 2.65 | 1.2 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | 下载 | 下载 | 下载 | 下载 | 下载 | 下载 | 下载 | 下载 |
参数化
| Parameters / Models | SN74LVTH241DBR | SN74LVTH241DW | SN74LVTH241DWR | SN74LVTH241DWRG4 | SN74LVTH241PW | SN74LVTH241PWE4 | SN74LVTH241PWG4 | SN74LVTH241PWR |
|---|---|---|---|---|---|---|---|---|
| Bits | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 |
| F @ Nom Voltage(Max), Mhz | 160 | 160 | 160 | 160 | 160 | 160 | 160 | 160 |
| ICC @ Nom Voltage(Max), mA | 0.005 | 0.005 | 0.005 | 0.005 | 0.005 | 0.005 | 0.005 | 0.005 |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Drive (IOL/IOH)(Max), mA | -32/64 | -32/64 | -32/64 | -32/64 | -32/64 | -32/64 | -32/64 | -32/64 |
| Package Group | SSOP | SOIC | SOIC | SOIC | TSSOP | TSSOP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 20SSOP: 56 mm2: 7.8 x 7.2(SSOP) | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) |
| Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
| Schmitt Trigger | No | No | No | No | No | No | No | No |
| Technology Family | LVT | LVT | LVT | LVT | LVT | LVT | LVT | LVT |
| VCC(Max), V | 3.6 | 3.6 | 3.6 | 3.6 | 3.6 | 3.6 | 3.6 | 3.6 |
| VCC(Min), V | 2.7 | 2.7 | 2.7 | 2.7 | 2.7 | 2.7 | 2.7 | 2.7 |
| Voltage(Nom), V | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 | 3.3 |
| tpd @ Nom Voltage(Max), ns | 4.1 | 4.1 | 4.1 | 4.1 | 4.1 | 4.1 | 4.1 | 4.1 |
生态计划
| SN74LVTH241DBR | SN74LVTH241DW | SN74LVTH241DWR | SN74LVTH241DWRG4 | SN74LVTH241PW | SN74LVTH241PWE4 | SN74LVTH241PWG4 | SN74LVTH241PWR | |
|---|---|---|---|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
应用须知
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, 档案已发布: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed. - Bus-Hold CircuitPDF, 418 Kb, 档案已发布: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
模型线
系列: SN74LVTH241 (8)
制造商分类
- Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver