Datasheet Texas Instruments SN75LVDS82DGGRG4 — 数据表

制造商Texas Instruments
系列SN75LVDS82
零件号SN75LVDS82DGGRG4
Datasheet Texas Instruments SN75LVDS82DGGRG4

FlatLink™接收器56-TSSOP 0至70

数据表

SN75LVDS82 FlatLinkв„ў Receiver datasheet
PDF, 1.5 Mb, 修订版: J, 档案已发布: Oct 24, 2016
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

打包

Pin56
Package TypeDGG
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingSN75LVDS82
Width (mm)6.1
Length (mm)14
Thickness (mm)1.15
Pitch (mm).5
Max Height (mm)1.2
Mechanical Data下载

参数化

Operating Temperature Range0 to 70 C
Package GroupTSSOP
Package Size: mm2:W x L56TSSOP: 113 mm2: 8.1 x 14(TSSOP) PKG
ProtocolsChannel-Link I
RatingCatalog
Supply Voltage(s)3.3 V

生态计划

RoHSCompliant

应用须知

  • FlatLinkв„ў Data Transmission System Using SN75LVDS83B/SN75LVDS82/SN75LVDS86A
    PDF, 333 Kb, 档案已发布: Feb 2, 2010
    This application report presents various system designs possible using the FlatLinkв„ў transmitter:SN75LVDS83B, and the FlatLinkв„ў receivers: SN75LVDS82 and SN75LVDS86A. These are low-voltagedifferential signaling (LVDS) serializer/deserializer (SerDes) devices commonly used to transmit video datato liquid crystal display (LCD) panels. The application report starts with an introduction of the F
  • Time Budgeting of the Flatlink Interface Application Report
    PDF, 99 Kb, 档案已发布: Jun 11, 1997
    This document describes the FlatLinkE point-to-point data-transmission interface that provides better than a two-to-one reduction in the number of signal lines used for synchronous parallel data-bus structures.
  • Flatlink Data Transmission System Design Overview (Rev. A)
    PDF, 127 Kb, 修订版: A, 档案已发布: Jun 1, 2001
    FlatLink is a data transmission system that can provide better than a 2:1 reduction in the number of signal lines used for synchronous parallel data bus structures with no loss in data throughput. To do this, FlatLink takes single-ended data at clock rates of up to 68 MHz and increases the data signaling rate seven times up to 476 Mbps. The following report provides some design guidelinesfo

模型线

制造商分类

  • Semiconductors > Interface > LVDS/M-LVDS/PECL > SerDes/Channel-Link