Datasheet Texas Instruments SN75LVDS86DGG — 数据表
| 制造商 | Texas Instruments |
| 系列 | SN75LVDS86 |
| 零件号 | SN75LVDS86DGG |
FlatLink™接收器48-TSSOP 0至70
数据表
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 48 |
| Package Type | DGG |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 40 |
| Carrier | TUBE |
| Device Marking | SN75LVDS86 |
| Width (mm) | 6.1 |
| Length (mm) | 12.5 |
| Thickness (mm) | 1.15 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
参数化
| Operating Temperature Range | 0 to 70 C |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG |
| Protocols | Channel-Link I |
| Rating | Catalog |
| Supply Voltage(s) | 3.3 V |
生态计划
| RoHS | Compliant |
应用须知
- Time Budgeting of the Flatlink Interface Application ReportPDF, 99 Kb, 档案已发布: Jun 11, 1997
This document describes the FlatLinkE point-to-point data-transmission interface that provides better than a two-to-one reduction in the number of signal lines used for synchronous parallel data-bus structures. - Flatlink Data Transmission System Design Overview (Rev. A)PDF, 127 Kb, 修订版: A, 档案已发布: Jun 1, 2001
FlatLink is a data transmission system that can provide better than a 2:1 reduction in the number of signal lines used for synchronous parallel data bus structures with no loss in data throughput. To do this, FlatLink takes single-ended data at clock rates of up to 68 MHz and increases the data signaling rate seven times up to 476 Mbps. The following report provides some design guidelinesfo
模型线
系列: SN75LVDS86 (3)
- SN75LVDS86DGG SN75LVDS86DGGG4 SN75LVDS86DGGR
制造商分类
- Semiconductors > Interface > LVDS/M-LVDS/PECL > SerDes/Channel-Link